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參數(shù)資料
| 型號： | ICE2A380P2 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS⑩ |
| 中文描述： | ⑩離線開關(guān)電源電流模式控制器，集成了800V的的CoolMOS |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 463K |
| 代理商： | ICE2A380P2 |
Version 0.0
8
23 Sep 2004
CoolSET-F2
ICE2A380P2
Functional Description
The primary current is sensed by the external series
resistor R
Sense
inserted in the source of the integrated
CoolMOS. By means of Current Mode regulation, the
secondary output voltage is insensitive on line
variations. Line variation changes the current
waveform slope which controls the duty cycle.The
external R
Sense
allows an individual adjustment of the
maximum source current of the integrated CoolMOS.
Figure 6
Improved Current Mode
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T
2
, the voltage source V
1
and the 1st order
low pass filter composed of R
1
and C
1
(see Figure 6,
Figure 7). Every time the oscillator shuts down for max.
duty cycle limitation the switch T2 is closed by V
OSC
.
When the oscillator triggers the Gate Driver T2 is
opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the Comparator C5, the Gate Driver is
switched-off until the voltage ramp exceeds 0.3V. It
allows the duty cycle to be reduced continuously till 0%
by decreasing V
FB
below that threshold.
Figure 7
Light Load Conditions
3.2.1
PWM-OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
R
Sense
connected to pin Isense. R
Sense
converts the
source current into a sense voltage. The sense voltage
is amplified with a gain of 3.65 by PWM OP. The output
of the PWM-OP is connected to the voltage source V1.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator, C5 and the Soft-Start-Comparator.
3.2.2
PWM-Comparator
The PWM-Comparator compares the sensed current
signal of the integrated CoolMOS
TM
with the feedback
signal V
FB
(see Figure 8). V
FB
is created by an external
optocoupler or external transistor in combination with
the internal pull-up resistor R
FB
and provides the load
information of the feedback circuitry. When the
amplified current signal of the integrated CoolMOS
exceeds the signal V
FB
the PWM-Comparator switches
off the Gate Driver.
x3.65
PWM OP
0.8V
10k
Oscillator
PWM Comparator
20pF
T
2
R
1
C
1
FB
PWM-Latch
V
1
C5
0.3V
Gate Driver
Voltage Ramp
V
OSC
Soft-Start Comparator
t
t
V
OSC
0.8V
FB
t
max.
Duty Cycle
0.3V
Gate Driver
Voltage Ramp
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| ICE2A765P2 | 功能描述:初級與次級側(cè) PWM 控制器 Off-Line SMPS Currnt Mode CTRLR 650V RoHS:否 制造商:ON Semiconductor 輸出端數(shù)量:1 開關(guān)頻率:250 KHz 工作電源電壓:- 0.3 V to + 28 V 最大工作溫度:+ 85 C 最小工作溫度:- 5 C 封裝 / 箱體:SOIC-8 Narrow 封裝:Reel |
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