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參數(shù)資料
| 型號(hào)： | ICE2A380P2 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS⑩ |
| 中文描述： | ⑩離線開(kāi)關(guān)電源電流模式控制器，集成了800V的的CoolMOS |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大?。?/td> | 463K |
| 代理商： | ICE2A380P2 |
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Version 0.0
10
23 Sep 2004
CoolSET-F2
ICE2A380P2
Functional Description
Figure 11
Start Up Phase
3.4
Oscillator and Frequency
Reduction
3.4.1
Oscillator
The oscillator generates a frequency f
= 100kHz. A
resistor, a capacitor and a current source and current
sink which determine the frequency are integrated. The
charging and discharging current of the implemented
oscillator capacitor are internally trimmed, in order to
achieve a very accurate switching frequency. The ratio
of controlled charge to discharge current is adjusted to
reach a max. duty cycle limitation of D
max
=0.72.
3.4.2
Frequency Reduction
The frequency of the oscillator is depending on the
voltage at pin FB. The dependence is shown in Figure
12. This feature allows a power supply to operate at
lower frequency at light loads thus lowering the
switching losses while maintaining good cross
regulation performance and low output ripple. In case
of low power the power consumption of the whole
SMPS can now be reduced very effective. The minimal
reachable frequency is limited to 21.5 kHz to avoid
audible noise in any case.
Figure 12
Frequency Dependence
3.5
Current Limiting
There is a cycle by cycle current limiting realized by the
Current-Limit Comparator to provide an overcurrent
detection. The source current of the integrated
CoolMOS
TM
is sensed via an external sense resistor
R
Sense
. By means of R
Sense
the source current is
transformed to a sense voltage V
Sense
. When the
voltage V
Sense
exceeds the internal threshold voltage
V
csth
the Current-Limit-Comparator immediately turns
off the gate drive. To prevent the Current Limiting from
distortions caused by leading edge spikes a Leading
Edge Blanking is integrated at the Current Sense.
Furthermore a Propagation Delay Compensation is
added to support the immediate shut down of the
CoolMOS in case of overcurrent.
3.5.1
Leading Edge Blanking
Figure 13
Leading Edge Blanking
Each time when CoolMOS is switched on a leading
spike
is
generated
due
capacitances and secondary-side rectifier reverse
recovery time. To avoid a premature termination of the
switching pulse this spike is blanked out with a time
constant of t
LEB
= 220ns. During that time the output of
to
the
primary-side
t
t
V
SoftS
t
5.3V
4.8V
T
Soft-Start
V
OUT
V
FB
V
OUT
T
Start-Up
100kHz
21.5kHz
21.5
65
100
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
kHz
V
FB
V
f
O
f
norm
f
standby
t
V
Sense
V
csth
t
LEB
= 220ns
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