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參數(shù)資料
| 型號(hào)： | ICD2051 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Dual Programmable Clock Generator(雙路可編程時(shí)鐘產(chǎn)生器) |
| 中文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 111K |
| 代理商： | ICD2051 |
Dual Programmable Clock Generator
ICD2051
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
January 1995 - Revised April 1995
408-943-2600
Features
Two independent clock outputs ranging from 320 kHz
to 100 MHz
Individually programmable PLLs use 22-bit serial word
Low-skew
÷
1,
÷
2, and
÷
4 CLKA outputs
Phase-locked loop oscillator input derived from exter-
nal low-frequency reference clock (1 MHz - 25 MHz) or
external crystal (2 MHz - 24 MHz)
Sophisticated internal loop-filter requires no external
components or manufacturing tweaks as commonly re-
quired with external filters
Three-state control disables outputs for test purposes
(optional)
5V operation
Low-power, high-speed CMOS technology
Available in 16-pin SOIC package
Functional Description
The ICD2051 Programmable Clock Generator offers two fully
user-programmable phase-locked loops in a single package.
The outputs may be changed “on the fly” to any desired fre-
quency value between 320 kHz and 100 MHz. The ICD2051
is ideally suited for any design where one or more multiple or
varying frequencies are required, thus replacing more expen-
sive metal can oscillators.
The capability to dynamically change the output frequency
adds a whole new degree of freedom for the electrical engi-
neer. Some examples of the uses for this device include: lap-
top computers, in which slowing the speed of operation can
mean less power consumption or speeding it up can mean
faster operation; graphics board dot clocks to allow dynamic
synchronization with different brands of monitors or display
formats; and on-board test strategies where the ability to
skew a system’s desired frequency (for example
±
10%) al-
lows worst case evaluations.
Logic Block Diagram
μ
Code
Decode
XTALOUT
OEA
VCO
Charge
Pump
Phase
Detector
÷
2p
PLL
SectionB
Internal Loop Filter
Phase-Locked Loop Oscillator Section A
GND V
DD
7
7
÷
q
f
(REF)
XTALIN
CLKA
XBUF
ICD2051–1
3
4
post-VCO divider select
VCO range select
MUX
MUXREFA
÷
2
÷
4
CLKA/2
CLKA/4
MUX
CLKB
Serial
Rcvr A
22
SCLKA
DATA
Serial
Rcvr B
22
SCLKB
MUXREFB
OEB
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