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2513L–AVR–03/2013
ATmega162/V
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f
ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High:> 2 CPU clock cycles for f
ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
SPI Serial
Programming
Algorithm
When writing serial data to the ATmega162, data is clocked on the rising edge of SCK.
When reading data from the ATmega162, data is clocked on the falling edge of SCK. See
FigureTo program and verify the ATmega162 in the SPI Serial Programming mode, the following
sequence is recommended (See four byte instruction formats in
Table 110):
1.
Power-up sequence:
Apply power between V
CC and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during Power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2.
Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming
Enable serial instruction to pin MOSI.
3.
The SPI Serial Programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4.
The Flash is programmed one page at a time. The page size is found in
Table 105 onpage 236. The memory page is loaded one byte at a time by supplying the 6 LSB of the
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for a given address. The Program Memory Page is stored by loading the Write
Program Memory Page instruction with the 8 MSB of the address. If polling is not used,
the user must wait at least t
WD_FLASH before issuing the next page. (See Table 109.) Accessing the SPI serial programming interface before the Flash write operation com-
pletes can result in incorrect programming.
5.
The EEPROM array can either be programmed one page at a time or it can be pro-
grammed byte by byte.
For Page Programming, the following algorithm is used:
The EEPROM memory page is loaded one byte at a time by supplying the 2 LSB of the
address and data together with the Load EEPROM Memory Page instruction. The EEPROM
Memory Page is stored by loading the Write EEPROM Memory Page instruction with the 8
MSB of the address. If polling is not used, the user must wait at least t
WD_EEPROM before issu-
ing the next page. (See
Table 99.) Accessing the SPI Serial Programming interface before
the EEPROM write operation completes can result in incorrect programming.
Alternatively, the EEPROM can be programmed bytewise:
The EEPROM array is programmed one byte at a time by supplying the address and data
together with the Write EEPROM instruction. An EEPROM memory location is first automat-
ically erased before new data is written. If polling is not used, the user must wait at least
t
WD_EEPROM before issuing the next byte. (See Table 109.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
6.
Any memory location can be verified by using the Read instruction which returns the con-
tent at the selected address at serial output MISO.