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參數(shù)資料
| 型號： | IC43R32400-5B |
| 英文描述： | 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| 中文描述： | 100萬× 32位× 4個銀行（128兆位）DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 3877K |
| 代理商： | IC43R32400-5B |
IC43R32400
6
Integrated Circuit Solution Inc.
DDR003-0B 11/10/2004
V
SS
V
DDQ
V
SSQ
V
REF
NC
Supply
Supply
Supply
Supply
-
Ground:
Ground
for the input buffers and core logic
.
DQ Power:
Provide isolated power to DQs for improved noise immunity.
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
Reference Voltage for Inputs:
+0.5 x V
DDQ
No Connect:
These pins should be left unconnected.
Note:
The timing reference point for the differential clocking is the cross point of the CK and CK#. For any applications
using the single ended clocking, apply V
REF
to CK# pin.
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and Auto Precharge Active
(3)
A0~A7
Read
Active
(3)
H
Read and Autoprecharge Active
(3)
H
A0~A7
Mode Register Set
Idle
H
State CKEn-1 CKEn DM BA1
Idle
(3)
H
Any
H
Any
H
Active
(3)
H
H
BA0 A8 A11-A9,A7-0 CS#
V Row address
V L
X H
V L
V H
RAS# CAS# WE#
L
H
L
H
L
H
H
L
H
L
X
X
X
X
X
X
X
X
V
V
V
V
X
V
V
L
L
L
L
L
H
L
L
L
L
X
X
X
X
X
X
V
V
V L
V H
L
L
H
H
L
L
H
H
X
X
X
X
X
X
X
X
X
L L
L H OP code L
X
X
X X L
X
X
X X H
X
X
X X L
X
X X X L L L H
X
X
X X L
X
X
X X H
L
X
X
X X H X X X
L
X
X
X X H X
L
X
X
X X X
X
X
X X X
OP code
L
L
L
H
X
H
L L
L L
H
X
H
Extended Mode Register Set
Idle H X
No-Operation
Device Deselect
Burst Stop Any
(4)
H
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
(SelfRefresh)
Power Down Mode Entry
Any
Any
H
H
X
X
X
H
L
H
H
X
L
Idle
Idle
Idle
H
H
L
L
X
H
L
X
H
H
X
H
Idle/Active
(5)
H
L
X
H
H
X
H H
X
X
H
X
Power Down Mode Exit
Any
L
H
X
(PowerDown)
Data Write/Output Enable Active
Data Mask/Output Disable Active
H
X
X
H
H
X
X
L
H
X
X
Column
address
Column
address
Note:
1. V =Valid Data, X =Don ’t care,L =Low level, H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA1 signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle,device state is clock suspend mode.
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2 shows the
truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
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| IC43R32400-5BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
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