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參數(shù)資料
| 型號： | IC42S81600L-7TIG |
| 英文描述： | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 4（2）M中的x 8（16）位× 4銀行（128 - Mbit的）同步動態(tài)RAM |
| 文件頁數(shù)： | 7/69頁 |
| 文件大?。?/td> | 1118K |
| 代理商： | IC42S81600L-7TIG |
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IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Integrated Circuit Solution Inc.
15
DR023-0E 6/11/2004
CKE RELATED COMMAND TRUTH TABLE(1)
CKE
Current State
Operation
n-1
n
CS
RAS
CAS
WE
Address
Self-Refresh (S.R.)
INVALID, CLK (n - 1)would exit S.R.
HX
X
Self-Refresh Recovery(2)
LH
H
X
Self-Refresh Recovery(2)
LH
L
H
X
Illegal
L
H
L
H
L
X
Illegal
L
H
L
X
Maintain S.R.
LL
X
Self-Refresh Recovery
Idle After tRC
HH
H
X
Idle After tRC
HH
L
H
X
Illegal
H
L
H
L
X
Illegal
H
L
X
Begin clock suspend next cycle(5)
HL
H
X
Begin clock suspend next cycle(5)
HL
L
H
X
Illegal
H
L
H
L
X
Illegal
H
L
X
Exit clock suspend next cycle(2)
LH
X
Maintain clock suspend
LL
X
Power-Down (P.D.)
INVALID, CLK (n - 1) would exit P.D.
HX
X
—
EXIT P.D.
→ Idle(2)
LH
X
Maintain power down mode
LL
X
Both Banks Idle
Refer to operations in Operative Command Table
HH
H
X
—
Refer to operations in Operative Command Table
HH
L
H
X
—
Refer to operations in Operative Command Table
HH
L
H
X
—
Auto-Refresh
H
L
H
X
Refer to operations in Operative Command Table
H
LLLL
Op - Code
Refer to operations in Operative Command Table
HL
H
X
—
Refer to operations in Operative Command Table
HL
L
H
X
—
Refer to operations in Operative Command Table
HL
L
H
X
—
Self-Refresh(3)
H
L
LLL
H
X
Refer to operations in Operative Command Table
H
L
LLLL
Op - Code
Power-Down(3)
LX
X
Any state
Refer to operations in Operative Command Table
HH
X
other than
Begin clock suspend next cycle(4)
HL
X
listed above
Exit clock suspend next cycle
LH
X
Maintain clock suspend
LL
X
Notes:
1. H : Hight level, L : low level, X : High or low level (Don’t care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied
before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSREX is not satisfied.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S81600L-8T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-8T(G) | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-8TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-8TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-8TI(G) | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
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