參數(shù)資料
型號: IC42S32800L-7TI
英文描述: 2M x 32 Bit x 4 Banks (256-MBIT) SDRAM
中文描述: 200萬× 32位× 4個銀行(256兆)內(nèi)存
文件頁數(shù): 22/62頁
文件大?。?/td> 879K
代理商: IC42S32800L-7TI
IC42S32800
IC42S32800L
22
Integrated Circuit Solution Inc.
DR046-0B 12/21/2004
- 6/7
Symbol
t
RC
A.C. Parameter
Min.
Max.
Unit
Note
Row cycle time
(same bank)
Row activate to row activate delay
(different banks)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command
(same bank)
Row activate to precharge time
(same bank)
Clock cycle time
60/70
9
t
RRD
12/14
9
t
RCD
15/20
9
t
RP
15/20
9
t
RAS
42/45
120,000
9
t
CK2
t
CK3
CL* = 2
CL* = 3
7.5/10
6/7
ns
Access time from CLK
(positive edge)
Data output hold time
9
t
AC
5.5/5.5
t
OH
2/2
9
t
CH
Clock high time
2.5/2.5
10
t
CL
Clock low time
2.5/2.5
10
t
IS
Data/Address/Control Input set-up time
1.5/1.5
10
t
IH
Data/Address/Control Input hold time
0.8
10
t
LZ
Data output low impedance
1
9
8
t
HZ
Data output high impedance
Write Recovery Time
CAS# to CAS# Delay time
Mode Register Set cycle time
5.4
t
WR
t
CCD
t
MRS
2
1
2
CLK
* CL is CAS# Latency.
Electrical Characteristics and Recommended A.C.Operating Conditions
(VDD =3.3V
±
0.3V,Ta =0~70 C)(Note:5,6,7,8)
Note:
1. Stress greater than those listed under “Absolute Maximum Ratings”may cause permanent damage to the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of
tCK and tRC.Input signals are changed one time during tCK.
4. These parameters depend on the output loading.Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
相關PDF資料
PDF描述
IC42S32800L-7TIG 2M x 32 Bit x 4 Banks (256-MBIT) SDRAM
IC43R32400 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM
IC43R32400-4B 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM
IC43R32400-4BG 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM
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