參數(shù)資料
型號: IC42S32800L-7TI
英文描述: 2M x 32 Bit x 4 Banks (256-MBIT) SDRAM
中文描述: 200萬× 32位× 4個銀行(256兆)內(nèi)存
文件頁數(shù): 21/62頁
文件大小: 879K
代理商: IC42S32800L-7TI
IC42S32800
IC42S32800L
Integrated Circuit Solution Inc.
DR046-0B 12/21/2004
21
- 6/7
Max.
Description/Test condition
Symbol
Unit
Note
Operating Current
t
RC
t
RC
(min), Outputs Open, Input
signal one transition per one cycle
Precharge Standby Current in power down mode
t
CK
= 15ns, CKE
V
IL
(max)
Precharge Standby Current in power down mode
t
CK
=
, CKE
V
IL
(max)
Precharge Standby Current in non-power down mode
t
CK
= 15ns, CS#
V
IH
(min), CKE
V
Input signals are changed once during 30ns.
Precharge Standby Current in non-power down mode
t
CK
=
, CLK
V
IL
(max), CKE
V
IH
Active Standby Current in power down mode
C KE
V
IL
(max), t
CK
= 15ns
Active Standby Current in power down mode
CKE& CLK
V
IL
(max), t
CK
=
Active Standby Current in non-power down mode
CKE
V
IH
(min), CS#
V
IH
(min), t
CK
= 15ns
Active Standby Current in non-power down mode
CKE
V
IH
(min), CLK
V
IL
(max), t
CK
=
Operating Current (Burst mode)
t
CK
=t
CK
(min),
Outputs Open, Multi-bank interleave
Refresh Current
t
RC
t
RC
(min)
Self Refresh Current
C KE
0.2V
1 bank
operation
I
CC1
135/125
3
I
CC2P
3
I
CC2PS
2
I
CC2N
20
3
I
CC2NS
9
I
CC3P
4
mA
3
I
CC3PS
3
I
CC3N
45
I
CC3NS
30
I
CC4
180/150
3, 4
I
CC5
300/270
3
I
CC6
1 (L-Version)
3
Parameter
Description
Min.
Max.
Unit
Note
I
IL
Input Leakage Current
(0V
V
IN
V
DD
, All other pins not under test = 0V )
Output Leakage Current
(0V
V
OUT
V
DD
, DQ disable )
- 1
+ 1
μ
A
I
OL
2.4
V
V
OH
LVTTL Output "H" Level Voltage
( I
OUT
= -2mA )
LVTTL Output "L" Level Voltage
( I
OUT
= 2mA )
3
3
V
OL
0.4
V
- 1.5
+ 1.5
μ
A
Recommended D.C.Operating Conditions (VDD =3.3V
±
0.3V,Ta =0~70 C)
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