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參數(shù)資料
| 型號： | IC42S32800L-6BG |
| 英文描述： | 2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
| 中文描述： | 200萬× 32位× 4個(gè)銀行（256兆）內(nèi)存 |
| 文件頁數(shù)： | 9/62頁 |
| 文件大?。?/td> | 879K |
| 代理商： | IC42S32800L-6BG |
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IC42S32800
IC42S32800L
Integrated Circuit Solution Inc.
DR046-0B 12/21/2004
9
T0
T2
T1
T3
T4
T5
T6
T7
T8
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
CLK
COMMAND
CAS# latency=2
tCK2, DQs
CAS# latency=3
tCK3, DQs
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B3
2
DOUT B
CLK
COMMAND
CAS# latency=2
tCK2, DQs
CAS# latency=3
tCK3, DQs
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst Read Operation(Burst Length =4,CAS#Latency =2,3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.DQM latency is two clocks
for output buffers).A read burst without the auto precharge function may be interrupted by a subsequent Read or Write
command to the same bank or the other active bank before the end of the burst length.It may be interrupted by a
BankPrecharge/PrechargeAll command to the same bank too.The interrupt coming from the Read command can occur on
any clock cycle following a previous Read command (refer to the following figure).
Read Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command.The
DQMs must be asserted (HIGH)at least two clocks prior to the Write command to suppress data-out on the DQ pins.To
guarantee the DQ pins against I/O contention,a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write command (refer to the following three figures).If the data output of the burst read occurs at the
second clock of the burst write,the DQMs must be asserted (HIGH)at least one clock prior to the Write command to avoid
internal bus contention.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC42S32800L-6BI | 2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
| IC42S32800L-6BIG | 2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
| IC42S32800L-6T | 2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
| IC42S32800L-6TG | 2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
| IC42S32800L-6TI | 2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S32800L-6BI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
| IC42S32800L-6BIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
| IC42S32800L-6T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
| IC42S32800L-6TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
| IC42S32800L-6TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:2M x 32 Bit x 4 Banks (256-MBIT) SDRAM |
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