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參數(shù)資料
| 型號： | IC42S32400L-7T |
| 英文描述： | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| 中文描述： | 100萬× 32位× 4個(gè)銀行（128兆）內(nèi)存 |
| 文件頁數(shù)： | 7/62頁 |
| 文件大?。?/td> | 899K |
| 代理商： | IC42S32400L-7T |
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IC42S32400
IC42S32400L
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005
7
Commands
1
BankActivate
(RAS#=”L”,CAS#=”H”,WE#=”H”,BS =Bank,A0-A11 =Row Address)
The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal.By latching the
row address on A0 to A11 at the time of this command,the selected row access is initiated.The read or write
operation in the same bank can occur after a time delay of tRCD(min.)from the time of bank activation.A
subsequent BankActivate command to a different row in the same bank can only be issued after the previous
active row has been precharged (refer to the following figure).The minimum time interval between successive
BankActivate commands to the same bank is defined by tRC(min.).The SDRAM has four internal banks on the
same chip and shares part of the internal circuitry to reduce chip area;therefore it restricts the back-to-back
activation of the four banks.tRRD(min.)specifies the minimum time required between activating different banks.
After this command is used,the Write command and the Block Write command perform the no mask write
operation.
T0
T1
T2
T3
CLK
ADDRESS
Tn+3
Tn+4
Tn+5
Tn+6
..............
COMMAND
..............
..............
NOP
NOP
NOP
NOP
RAS# - CAS# delay (
t
RCD
)
RAS#- RAS# delay time (
t
RRD
)
RAS# Cycle time (
t
RC
)
RBank A
Bank A
RBank B
RBank A
Bank A
R/W A with
AutoPrecharge
Bank B
Bank A
Auto Precharge
Begin
:"H" or "L"
Bank
2
BankPrecharge command
(RAS#=”L”,CAS#=”H”,WE#=”L”,BS =Bank,A10 =”L”)
The BankPrecharge command precharges the bank disignated by BS0,1 signal.The
precharged bank is switched from the active state to the idle state.This command can be asserted anytime after
tRAS(min.)is satisfied from the BankActivate command in the desired bank.The maximum time any bank can be
active is specified by tRAS(max.).Therefore,the precharge function must be performed in any active bank within
tRAS(max.).At the end of precharge,the precharged bank is still in the idle state and is ready to be activated again.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC42S32400L-7TG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7TI | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7TIG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-8B | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-8BG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S32400L-7TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-8B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-8BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
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