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參數(shù)資料
| 型號： | IC42S32400L-7T |
| 英文描述： | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| 中文描述： | 100萬× 32位× 4個銀行（128兆）內(nèi)存 |
| 文件頁數(shù)： | 23/62頁 |
| 文件大?。?/td> | 899K |
| 代理商： | IC42S32400L-7T |
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IC42S32400
IC42S32400L
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005
23
6.A.C.Test Conditions
LVTTL Interface
Reference Level of Output Signals
Output Load
Input Signal Levels
Transition Time (Rise and Fall)of Input Signals
Reference Level of Input Signals
1.4V /1.4V
Reference to the Under Output Load (B)
2.4V /0.4V
1ns
1.4V
3.3V
1.2k
870
30pF
Output
LVTTL D.C. Test Load (A)
1.4V
50
Output
30pF
Z0=
50
LVTTL A.C. Test Load (B)
7.
Transition times are measured between VIH and VIL.Transition(rise and fall)of input signals are in a fixed slope
(1 ns).
t
HZ
defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
If clock rising time is longer than 1 ns,(t
R
/2 -0.5)ns should be added to the parameter.
10. Assumed input rise and fall time t
T
(t
R
&t
F
)=1 ns
If t
R
or t
F
is longer than 1 ns,transient time compensation should be considered,i.e.,[(tr +tf)/2 -1 ]ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to V
DD
and V
DDQ
(simultaneously)when all input signals are held “NOP”state
and both CKE =”H”and DQM =”H.”The CLK signals must be started at the same
time.
2) After power-up,a pause of 200
μ
seconds minimum is required.Then,it is recom
mended that DQM is held “HIGH”(V
DD
levels)to ensure DQ output is in high
impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
8.
9.
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| IC42S32400L-7TG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7TI | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7TIG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-8B | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-8BG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S32400L-7TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-8B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-8BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
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