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參數(shù)資料
| 型號： | IC42S16800L-6T(G) |
| 英文描述： | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 4（2）M中的x 8（16）位× 4銀行（128 - Mbit的）同步動態(tài)RAM |
| 文件頁數(shù)： | 14/69頁 |
| 文件大?。?/td> | 1118K |
| 代理商： | IC42S16800L-6T(G) |
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IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
14
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
OPERATION COMMAND TABLE
(continue)
Current State
Command
Operation
CS
RAS
CAS
WE
Address
Write
recovering
with auto
precharge
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
NOP
BST
READ/WRIT
ACT/PRE/PALL/
REF/SELF/MRS
Nop
→
Enter precharge after t
DPL
Nop
→
Enter precharge after t
DPL
Nop
→
Enter precharge after t
DPL
Illegal
(3 ,8, 11)
Illegal
(3,11)
Illegal
(3, 11)
Illegal
(3, 11)
Illegal
Illegal
Nop Enter idle after t
RC
Nop Enter idle after t
RC
Illegal
Illegal
Illegal
Nop
→
Enter idle after 2 Clocks
Nop
→
Enter idle after 2 Clocks
Illegal
Illegal
Illegal
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
L
L
X
H
H
H
L
X
H
H
L
L
H
H
L
L
X
H
L
H
L
X
H
H
L
X
X
H
L
H
L
H
L
H
L
X
X
X
X
X
X
H
L
X
X
X
X
X
BA, CA, A10
BA, CA, A10
BR, RA
BA, A10
X
Op-Code
X
X
X
X
X
X
X
X
X
X
Auto
Refreshing
Mode
register
setting
Notes:
1.
2.
All entries assume that CKE was active (High level) during the preceding clock cycle.
If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKE
will be disabled.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address(BA), depending on the
state of that bank.
If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE
will be disabled.
Illegal if t
RCD
is not satisfied.
Illegal if t
RAS
is not satisfied.
Must satisfy burst interrupt condition.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Must mask preceding data which don’t satisfy t
DPL
.
10. Illegal if t
RRD
is not satisfied.
11. Illegal for single bank, but legal for other banks in multi-bank devices.
3.
4.
5.
6.
7.
8.
9.
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| IC42S16800L-6TG | IC DUAL SPDT ANALOG SW 16-SOIC |
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| IC42S16800L-6TIG | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16800L-7T | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S16800L-6TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16800L-6TI(G) | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16800L-6TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16800L-7T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16800L-7T(G) | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
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