參數(shù)資料
型號： IBMN325804CT3
廠商： IBM Microeletronics
英文描述： 256Mb（8Mbit x 8 I/O x 4 Bank） Synchronous DRAM(256M位（8M位 x 8 I/O x 4 組）同步動態(tài)RAM)
中文描述： 256Mb的（8Mbit × 8的I / O × 4行）同步DRAM（256M位（800萬位× 8的I / O × 4組）同步動態(tài)RAM）的
文件頁數(shù)： 10/66頁
文件大?。?/td> 1699K
代理商： IBMN325804CT3
IBMN325164CT3
IBMN325404CT3
256Mb Synchronous DRAM - Die Revision B
IBMN325804CT3
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 66
06K0608.F39375A
10/00
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (t
RCD
). WE must also be
defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation
(WE low). The address inputs determine the starting column address.
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a
serial read or write operation on successive clock cycles up to 133 MHz. The number of serial data bits for
each access is equal to the burst length, which is programmed into the Mode Register.
Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers
latch the selected row address information. The refresh period (t
REF
) is what limits the number of random col-
umn accesses to an activated bank. A new burst access can be done even before the previous burst ends.
The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule.
When the previous burst is interrupted by another Read or Write Command, the remaining addresses are
overridden by the new address.
Precharging an active bank after each read or write operation is not necessary providing the same row is to
be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must
be precharged and a new Bank Activate command must be issued. When more than one bank is activated,
interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length
and alternating the access and precharge operations between multiple banks, fast and seamless data access
operation among many different pages can be realized. When multiple banks are activated, column to column
interleave operation can be done between different pages. Finally, Read or Write Commands can be issued
to the same bank or between active banks on every clock cycle.
相關(guān)PDF資料
PDF描述
IBMN325164CT3 256Mb（16Mbit x 4 I/O x 4 Bank） Synchronous DRAM(256M位（16M位 x 4 I/O x 4 組）同步動態(tài)RAM)
IBMN612404GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）)
IBMN612804GT3B 128Mb Double Data Rate Synchronous DRAM(128M位高速CMOS同步動態(tài)RAM（采用雙數(shù)據(jù)速率結(jié)構(gòu)）)
IBMN625404GT3B 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM)
IBMN625804GT3B 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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