參數(shù)資料
型號(hào)： IBMN325404CT3
廠商： IBM Microeletronics
英文描述： 256Mb（4Mbit x 16 I/O x 4 Bank） Synchronous DRAM(256M位（4M位 x 16 I/O x 4 組）同步動(dòng)態(tài)RAM)
中文描述： 256Mb的（的4Mb × 16的I / O × 4行）同步DRAM（256M位（4分位× 16的I / O × 4組）同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 3/66頁(yè)
文件大?。?/td> 1699K
代理商： IBMN325404CT3
IBMN325164CT3 IBMN325804CT3
IBMN325404CT3
Preliminary
256Mb Synchronous DRAM - Die Revision B
06K0608.F39375A
10/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 66
Pin Description
CK
Clock Input
DQ0-DQ15
Data Input/Output
CKE (CKE0, CKE1)
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS (CS0, CS1)
Chip Select
V
DD
Power (+3.3V)
RAS
Row Address Strobe
V
SS
Ground
CAS
Column Address Strobe
V
DDQ
Power for DQs (+3.3V)
WE
Write Enable
V
SSQ
Ground for DQs
BA1, BA0
Bank Select
NC
No Connection
A0 - A12
Address Inputs
—
—
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK
Input
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE, CKE0,
CKE1
Input
Active
High
Activates the CK signal when high and deactivates the CK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS, CS0, CS1
Input
Active Low
CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
RAS, CAS, WE
Input
Active Lowto be executed by the SDRAM.
BA1, BA0
Input
—
Selects which bank is to be active.
A0 - A12
Input
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9,
CA11), when sampled at the rising clock edge. Assume the x4 organization.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10
is high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is
low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If
A10 is low, then BA0 and BA1 are used to define which bank to precharge.
DQ0 - DQ15
Input-
Output
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DQM
LDQM
UDQM
Input
Active
High
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled
high. In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers,
respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buff-
ers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In
Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to
be written if it is low but blocks the write operation if DQM is high.
V
DD
, V
SS
Supply
—
Power and ground for the input buffers and the core logic.
V
DDQ
V
SSQ
Supply
—
Isolated power supply and ground for the output buffers to provide improved noise immunity.
.
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