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參數(shù)資料
| 型號： | IBMN325404CT3 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256Mb（4Mbit x 16 I/O x 4 Bank） Synchronous DRAM(256M位（4M位 x 16 I/O x 4 組）同步動(dòng)態(tài)RAM) |
| 中文描述： | 256Mb的（的4Mb × 16的I / O × 4行）同步DRAM（256M位（4分位× 16的I / O × 4組）同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 27/66頁 |
| 文件大?。?/td> | 1699K |
| 代理商： | IBMN325404CT3 |
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IBMN325164CT3
IBMN325804CT3
IBMN325404CT3
Preliminary
256Mb Synchronous DRAM - Die Revision B
06K0608.F39375A
10/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 27 of 66
Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When
the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately
(zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and
become high impedance after a two-clock delay, independent of CAS latency.
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The pur-
pose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands
between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held
high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is
still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command
occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.
Data Mask Activated during a Read Cycle
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQM
: “H” or “L”
A two-clock delay before
the DQs become Hi-Z
DQs
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT A
0
DOUT A
1
(Burst Length = 4, CAS Latency = 2)
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