參數(shù)資料
型號: IBM42M10LNYAA10
廠商: IBM Microeletronics
英文描述: 1063 MB/S Gigabit Link Module(1063 MB/S 吉位連接模塊(高性能集成光纖收發(fā)器))
中文描述: 1063 MB / s的千兆連接模塊(1063 MB /秒吉位連接模塊(高性能集成光纖收發(fā)器))
文件頁數(shù): 4/26頁
文件大?。?/td> 436K
代理商: IBM42M10LNYAA10
IBM42M10SNYAA20
IBM42M10LNYAA10
1063Mb/s Gigabit Link Module - No OFC
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 26
GLM1063N.02
11/10/99
Transmit Section
The 20-bit transmit data enters the shift register and is clocked out at 1062.5Mbit/s to the serial output pins
and the multiplexer. The AC Drive modulates the laser with the data from the Serial Input pins or the serial-
ized version of the Transmit Data. The Transmit Phase Locked Loop (Tx PLL) generates the internal
1062.5MHz Clock for the shift register from the 53.125MHz Transmit Byte Clock provided by the system. The
DC Drive maintains the laser at the correct preset power level. Safety circuits in the DC Drive will shut off the
laser if a fault is detected. The multiplexer is used to route the serialized data to the Receive Section while in
wrap mode.
Receive Section
The incoming, modulated optical signal is received by the photoreceiver. The Receive PLL (Rx PLL) phase
locks a 1062.5MHz Clock to the data and sends the data and clock to the shift register (S/R) to be deserial-
ized. The S/R has a byte synchronization detector that recognizes a unique Comma Character so that com-
plete bytes can be unloaded from the S/R without being fragmented. The Clock Generator creates two
complementary phases of a 53.125MHz Clock for use by the host system to latch the Receive Data.
Block Diagram
Shift Register
Shift Register
PLL
Pos&
MUX
Laser
Fiber
Input
Transition
Detector
Loss of
Light
Detector
GClock
Lck_Ref
L_Unuse
Fault
EWrap
AC Drive
Photo-
DC Drive
TBC
Output
Fiber
En_CDet
Com_Det
Fault
Rx
Tx PLL
Transition
Detector
RBC[0:1]
Tx[00:19]
Rx[00:19]
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