參數(shù)資料
型號: IBM39STB0210x
廠商: IBM Microeletronics
英文描述: STB0210x Digital Set-Top Box Integrated Controllers(用于數(shù)字STB應用的數(shù)字機頂盒集成控制器)
中文描述: STB0210x數(shù)字機頂盒集成控制器(用于數(shù)字機頂盒應用的數(shù)字機頂盒集成控制器)
文件頁數(shù): 1/39頁
文件大?。?/td> 503K
代理商: IBM39STB0210X
STB02_sds_0327.fm.01
March 27, 2000
IBM39STB0210x
Advance
STB0210x Digital Set-Top Box Integrated Controllers
Features
Page 1 of 39
Features
Overall
IBM Set-Top Box technology
Four major subsystems integrated with IBM on-
chip CoreConnect
structure.
Maximum MIPS for OS and application tasks
Simplified driver and software development
Scalable, flexible, and extendible
54 MHz/57 MIPS
3.3 V and 2.5 V power supplies
IBM CMOS SA-12E process(0.25
μ
m)
352-pin PBGA package
MPEG-2 Digital Audio/Video Subsystem
MPEG-2 Video Decoder
MPEG-2 Audio Decoder
MPEG-2 Transport/DVB Descrambler
Macrovision Copy Protection on selected parts
Display Controller
Digital Encoder (DENC) with six outputs
Anti-Flicker Filter
PowerPC 401
Host Processor: PPC401B3 CPU
16KB Instruction, 8KB Data caches
Universal Interrupt Controller
Memory Subsystem
DMA Controller
Cross-Bar Switch
External Bus Interface Unit (EBIU)
IDE Interface
One SDRAM Controller
Peripheral Subsystem
General Purpose Timers (GPTs)
Pulse Width Modulators
Smart Card controller
I
2
C Interface
16550 Serial Communications Port
Infrared Serial Communications Port
General Purpose Inputs/Outputs
Serial Controller Port
Modem Serial Interface/Digital Audio Input
Description
IBM STB0210x Digital Set-Top Box Integrated Con-
troller family are highly integrated silicon devices
specifically developed for digital set-top box (STB)
applications using industry-leading IBM CMOS SA-
12E (0.25
μ
m) process technology.
The STB0210x is part of the second generation of
IBM products for digital STB applications. PowerPC
processing and peripheral I/O architecture provide a
high level of performance and functionality when
used in audio and video subsystems. The resulting
STB technology is full-functioned and easy to use.
The STB0210x minimizes host processor interven-
tion to maximize MIPS for operating system and
application tasks. Most of the features required in
the back end of typical midrange and high-end
STBs are integrated. Driver and software develop-
ment is facilitated while preserving scaleability, flex-
ibility, and extendibility.
Architecturally, the devices consist of four sub-
systems interconnected and tuned using CoreCon-
nect, the IBM multiple-bus, on-chip interconnect
structure:
1. PowerPC host processor
2. Digital audio/video
3. Memory interface
4. Peripheral
These high performance subsystems are suited for
interactive STBs with demanding software require-
ments.
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