參數(shù)資料
型號(hào)： IBM25PPC750GXEBB5H43T
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 933 MHz, RISC PROCESSOR, CBGA292
封裝： 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292
文件頁(yè)數(shù)： 43/74頁(yè)
文件大?。?/td> 1054K
代理商： IBM25PPC750GXEBB5H43T
Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
System Design Information
Page 48 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
5.2.3 PLL_RNG[0:1] Definitions for Dual PLL Operation
The dual PLLs on the 750GX are configured by the PLL_CFG[0:4] and PLL_RNG[0:1] signals. For a given
SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and voltage controlled oscillator
(VCO) frequency of operation. The 750GX PLL range configuration for dual PLL operation is shown in the
following table.
5.2.4 PLL Configuration
Table 5-2 shows the PLL configuration for the 750GX for nominal frequencies.
Table 5-1. PLL_RNG[0:1] Definitions for Dual PLL Operation
PLL_RNG[0:1]
PLL Frequency Range
00 (default)
600 MHz–900 MHz
01 (fast)
900 MHz–1.0 GHz
10 (slow)
500 MHz–600 MHz
11 (reserved)
Reserved
Note: PLL_RNG bit settings are valid for a VDD range of 1.4 V–1.55 V and a temperature range of -40°C–105°C.
Table 5-2. 750GX Microprocessor PLL Configuration
PLL_CFG [0:4]
Processor to Bus
Frequency Ratio
(PTBFR)
Frequency Range Supported by VCO Having an Example Range of...
SYSCLK1 (MHz)
Core (MHz)
Binary
Decimal
Minimum
(SYSCLKMIN)
Maximum
(SYSCLKMAX)
Minimum
(Core FrequencyMIN)
Maximum
(Core FrequencyMAX)
00000
0
Off2
N/A
Off
00001
1
Off2
N/A
Off
00010
2
PLL Bypass3
N/A
00011
3
PLL Bypass3
N/A
00100
4
2×4
N/A
00101
5
2.5×4
200
500
00110
6
3×4
167
200
500
600
00111
7
3.5×4
143
200
500
700
01000
8
4×
125
200
500
800
01001
9
4.5×
111
200
500
900
01010
10
5×
100
200
500
1000
01011
11
5.5×
91
182
500
1000
01100
12
6×
83
166
500
1000
Notes:
1. The SYSCLK frequency equals the core frequency divided by the processor-to-bus frequency ratio (PTBFR).
2. In clock-off mode, no clocking occurs inside the 750GX regardless of the SYSCLK input.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set
for 1:1 mode operation. This mode is intended for factory use only.
The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. The 2×–3.5× processor-to-bus ratios are currently not supported when miss-under-miss is enabled (HID0(14) = '1').
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