參數(shù)資料
型號(hào)： IBM25PPC750FX-GB0123T
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 600 MHz, RISC PROCESSOR, CBGA292
封裝： 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292
文件頁(yè)數(shù)： 11/62頁(yè)
文件大?。?/td> 452K
代理商： IBM25PPC750FX-GB0123T
DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
3. Electrical and Thermal Characteristics
Page 17 of 63
3.5 60x Bus Output AC Specications
Table 3-8 provides the 60x bus output AC timing specifications for the 750FX as defined in Figure 3-6 on
Table 3-8. 60x Bus Output AC Timing Specications
See Table 3-2 on page 10 for operating conditions.1, 5
Num
Characteristic
1.8V
2.5V
3.3V
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
12
SYSCLK to Output Driven
(Output Enable Time)
0.3
—
0.3
—
0.3
—
ns
—
13
SYSCLK to Output Valid
—
2.3
—
2.5
—
2.5
ns
2, 6
14
SYSCLK to Output Invalid (Output Hold)
0.5
—
0.55
—
0.55
–
ns
2, 7
15
SYSCLK to Output High Impedance
(all signals except ARTRY, ABB and DBB)
—
2.5
—
2.5
—
2.5
ns
—
16
SYSCLK to ABB and DBB high impedance
after precharge
—
1.0
—
1.0
—
1.0
tSYSCLK
3, 4
17
SYSCLK to ARTRY high impedance
before precharge
—
3.0
—
3.0
—
3.0
ns
—
18
SYSCLK to ARTRY precharge enable
0.2
×
tSYSCLK +
1.0
0.2
×
tSYSCLK +
1.0
—
0.2
×
tSYSCLK +
1.0
—
ns
2, 3, 4
19
Maximum delay to ARTRY precharge
—
1.0
—
1.0
—
1.0
tSYSCLK
3, 4
20
SYSCLK to ARTRY high impedance
after precharge
—
2.0
tSYSCLK
3, 4
Notes:
1. All output specifications are measured from the VM of the rising edge of SYSCLK to the output signal level defined in Figure 3-5 on
page 18. Both input and output timings are measured at the pin. Timings are determined by design.
2. This minimum parameter assumes CL = 0pF.
3. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
by the period of SYSCLK to compute the actual time duration of the parameter in question.
4. Nominal precharge width for ARTRY is 1.0 tSYSCLK.
5. Guaranteed by design and characterization, and not tested.
6. Output Valid timing increases as the VDD in reduced. These values assumes VDD minimum of 1.35V.
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