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Data Sheet
PowerPC 750CXe RISC Microprocessor
Preliminary
General Information
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
Floating-point unit (continued)
- Hardware support for divide
- Hardware support for denormalized
numbers
- Time deterministic non-IEEE mode
System unit
- Executes CR logical instructions and
miscellaneous system instructions
- Special register transfer instructions
L1 Cache structure
- 32KB, 32-byte line, 8-way set associative
instruction cache
- 32KB, 32-byte line, 8-way set associative
data cache
- Single-cycle cache access
- Pseudo-LRU replacement
- Copy-back or write-through data cache (on
a page per page basis)
- 3-state (MEI) memory coherency
- Hardware support for data coherency
- Non-blocking instruction and data cache
(one outstanding miss under hits)
- No snooping of instruction cache
Memory management unit
- 128-entry, 2-way set associative instruction
TLB
- 128-entry, 2-way set associative data TLB
- Hardware reload for TLBs
- 4 instruction BATs and 4 data BATs
- Virtual memory support for up to 4 PB (252)
virtual memory
- Real memory support for up to 4 GB (232) of
physical memory
- Support for big/little-endian addressing
Level 2 (L2) cache
- Internal L2 cache controller and 4KB-entry
tags; 256KB data SRAMs
- Copy-back or write-through data cache on a
page basis, or for all L2
- 64-byte sectored line size
- L2 frequency at core speed
- On-board ECC
Bus interface
- Compatible with 60x processor interface
- 32-bit address bus
- 64-bit data bus (also supports 32-bit mode)
- Core-to-bus frequency multipliers of 3x,
3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,
8x, 9x, and 10x supported
Power
- Under 4W typical @ 400 MHz
Testability
- LSSD scan design
- Powerful diagnostic and test interface
through Common On-Chip Processor (COP)
and IEEE 1149.1 (JTAG) interface