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| 型號： | IBM25PPC750CX-CP30-3T |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 433 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 29/44頁 |
| 文件大?。?/td> | 562K |
| 代理商： | IBM25PPC750CX-CP30-3T |
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Page
35
Version
1.1
PowerPC
750CX
RISC
Microprocessor
Datasheet
November
13,
2000
SYSCLK
Low
IN
Clock Control
Keeper
No resistor by design
Active driver
TA
Low
IN
Data Termination
Keeper
Active driver
TBST
Low
BIDI
Transfer Attributes
Keeper
See Note 1
TCK
High
IN
JTAG
Not enabled
Ext. pulldown
TDI
High
IN
JTAG
Enabled high
Internal-
Enabled
50
a@2.5V, 25a@1.8V is the pullup
current for the internal resistor.
TDO
High
OUT
JTAG
Keeper
TEA
Low
IN
Data Termination
Keeper
Active driver or pullup
TMS
High
IN
JTAG
Enabled high
Internal-
Enabled
50
a@2.5V, 25a@1.8V is the pullup
current for the internal resistor.
TRST
Low
IN
JTAG
Enabled high
Internal-
Enabled
See Note 2
50
a@2.5V, 25a@1.8V is the pullup
current for the internal resistor.
TS
Low
BIDI
Address Start
Keeper
5K DD1.0, 2.0, 2.1, 2.2 Pullup required
TSIZ0_TSIZ2
N/A
OUT
Transfer Attributes
Keeper
See Note 1
TT0-4
N/A
IN
Transfer Attributes
Keeper
See Note 1
WT
Low
OUT
Transfer Attributes
Keeper
See Note 1
Table 16: Input-Output Usage (cont.)
PowerPC 750CX
Signal Name
Active
Level
Input/
Output
Usage Group
I/O with Internal
Resistors
Level Protect
Required External
Resistor
Comments
Note:
1. Depends on the system design
2. HRESET, SRESET, and TRST are signals used for ESP and RISCWatch to enable proper operation of the debuggers. Logical AND gates should be placed between these signals and PowerPC 750CX
RISC Microprocessor. (Refer to Figure 17 on page 36.)
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