參數(shù)資料
型號(hào)： IBM25PPC405GPR3DB266
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA456
封裝： 27 X 27 MM, ENHANCED, PLASTIC, BGA-456
文件頁(yè)數(shù)： 25/58頁(yè)
文件大?。?/td> 1264K
代理商： IBM25PPC405GPR3DB266
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
3/14/03
Page 31 of 58
PCIReq1:5
Used as PCIReq1:5 input when internal arbiter is used.
I
5V tolerant
3.3V PCI
PCIGnt0[Req]
Gnt0 when internal arbiter is used
or
Req when external arbiter is used.
O
5V tolerant
3.3V PCI
PCIGnt1:5
Used as PCIGnt1:5 output when internal arbiter is used.
O
5V tolerant
3.3V PCI
Ethernet Interface
PHYRxD3:0
Received data. This is a nibble wide bus from the PHY. The data
is synchronous with the PHYRxClk.
I
5V tolerant
3.3V LVTTL
1
EMCTxD3:0
Transmit data. A nibble wide data bus towards the net. The data
is synchronous to the PHYTxClk.
O
5V tolerant
3.3V LVTTL
6
PHYRxErr
Receive Error. This signal comes from the PHY and is
synchronous to the PHYRxClk.
I
5V tolerant
3.3V LVTTL
1
PHYRxClk
Receiver Medium clock. This signal is generated by the PHY.
I
5V tolerant
3.3V LVTTL
1
PHYRxDV
Receive Data Valid. Data on the Data Bus is valid when this
signal is activated. Deassertion of this signal indicates end of the
frame reception.
I
5V tolerant
3.3V LVTTL
1
PHYCrS
Carrier Sense signal from the PHY. This is an asynchronous
signal.
I
5V tolerant
3.3V LVTTL
1
EMCTxErr
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous with the
PHYTxClk. It informs the PHY that an error was detected.
O
5V tolerant
3.3V LVTTL
6
EMCTxEn
Transmit Enable. This signal is driven by the EMAC to the PHY.
Data is valid during the active state of this signal. Deassertion of
this signal indicates end of frame transmission. This signal is
synchronous to the PHYTxClk.
O
5V tolerant
3.3V LVTTL
6
PHYTxClk
This clock comes from the PHY and is the Medium Transmit
clock.
I
5V tolerant
3.3V LVTTL
1
PHYCol
Collision signal from the PHY. This is an asynchronous signal.
I
5V tolerant
3.3V LVTTL
1
EMCMDClk
Management Data Clock. The MDClk is sourced to the PHY. This
clock has a period of 400ns, adjustable via
EMAC0_STACR[OPBC]. Management information is transferred
synchronously with respect to this clock.
O
5V tolerant
3.3V LVTTL
EMCMDIO[PHYMDIO]
Management Data Input/Output is a bidirectional signal between
the Ethernet controller and the PHY. It is used to transfer control
and status information.
I/O
5V tolerant
3.3V LVTTL
1
Signal Functional Description (Part 2 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
Description
I/OType
Notes
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