參數(shù)資料
型號: IBM25PPC405GP-3DD200C
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA456
封裝: 27 MM, PLASTIC, BGA-456
文件頁數(shù): 46/58頁
文件大?。?/td> 878K
代理商: IBM25PPC405GP-3DD200C
PowerPC 405GP Embedded Processor Data Sheet
50
Peripheral Interface Clock Timings
Parameter
Min
Max
Units
PCIClk input frequency (asynchronous mode)
Note 1
66
MHz
PCIClk period (asynchronous mode)
15
Note 1
ns
PCI Clock frequency (synchronous mode)
25
33
MHz
PCI Clock period (synchronous mode - Note 2)
30
40
ns
PCIClk input high time
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
2.5
MHz
EMCMDClk period
400
ns
EMCMDClk output high time
160
ns
EMCMDClk output low time
160
ns
PHYTxClk input frequency
2.5
25
MHz
PHYTxClk period
40
400
ns
PHYTxClk input high time
35% of nominal period
ns
PHYTxClk input low time
35% of nominal period
ns
PHYRxClk input frequency
2.5
25
MHz
PHYRxClk period
40
400
ns
PHYRxClk input high time
35% of nominal period
ns
PHYRxClk input low time
35% of nominal period
ns
PerClk output frequency–200MHz (for external master or synchronous
slaves)
50
MHz
PerClk period–200MHz
20
ns
PerClk output frequency–266MHz (for external master or synchronous
slaves)
–66
PerClk period–266MHz
15
PerClk output high time
50% of nominal period
66% of nominal period
ns
PerClk output low time
33% of nominal period
50% of nominal period
ns
UARTSerClk input frequency (Note 3)
1000/(2TOPB+2ns)
MHz
UARTSerClk period
2TOPB+2
–ns
UARTSerClk input high time
TOPB+1
–ns
UARTSerClk input low time
TOPB+1
–ns
TmrClk input frequency–200MHz
50
MHz
TmrClk period–200MHz
20
ns
TmrClk input frequency–266MHz
66
TmrClk period–266MHz
15
TmrClk input high time
40% of nominal period
60% of nominal period
ns
TmrClk input low time
40% of nominal period
60% of nominal period
ns
Notes:
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PPC405GP User’s Manual for more
information.
2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
3. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB
clock frequency is 50 MHz for 200MHz parts and 66MHz.for 266MHz parts.
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