參數(shù)資料
型號(hào)： IBM25PPC405GP-3BE200C
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA456
封裝： 35 X 35 MM, ENHANCED, PLASTIC, BGA-456
文件頁(yè)數(shù)： 30/60頁(yè)
文件大小： 1480K
代理商： IBM25PPC405GP-3BE200C
PowerPC 405GP Embedded Processor Data Sheet
Page 36 of 60
6/20/03
SDRAM Interface
MemData0:31
Memory data bus.
Notes:
1. MemData0 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
I/O
3.3V LVTTL
MemAddr12:0
Memory address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr0 is the least significant bit (lsb).
O3.3V LVTTL
BA1:0
Bank Address supporting up to 4 internal banks.
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM0:3
DQM for byte lane: 0 (MemData0:7),
1 (MemData8:15),
2 (MemData16:23), and
3 (MemData24:31)
O3.3V LVTTL
DQMCB
DQM for ECC check bits.
O
3.3V LVTTL
ECC0:7
ECC check bits 0:7.
I/O
3.3V LVTTL
BankSel0:3
Select up to four external SDRAM banks.
O
3.3V LVTTL
WE
Write Enable.
O
3.3V LVTTL
ClkEn0:1
SDRAM Clock Enable.
O
3.3V LVTTL
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a
PLL or zero-delay buffer.
O3.3V LVTTL
External Slave Peripheral Interface
PerData0:31
Peripheral data bus used by PPC405GP when not in external
master mode, otherwise used by external master.
Note: PerData0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr0:31
Peripheral address bus used by PPC405GP when not in external
master mode, otherwise used by external master.
Note: PerAddr0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerPar0:3
Peripheral byte parity signals.
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:3
As outputs, these pins can act as byte-enables which are valid for
an entire cycle or as write-byte-enables which are valid for each
byte on each data transfer, allowing partial word transactions. As
outputs, pins are used by either the pripheral controller or the
DMA controller depending upon the type of transfer involved.
Used as inputs when an external bus master owns the external
interface.
I/O
5V tolerant
3.3V LVTTL
1, 7
Signal Functional Description (Part 3 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
PDF描述
IBM25PPC405GP-3EE266C 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA413
IBM25PPC405GP-3DE266CZ 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA456
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM25PPC405GP3BE200CZ 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|456PIN|PLASTIC
IBM25PPC405GP-3BE266C 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|456PIN|PLASTIC
IBM25PPC405GP3BE266CZ 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|456PIN|PLASTIC
IBM25PPC405GP-3DE200C 制造商:IBM 功能描述:Microprocessor, 32 Bit, 456 Pin, Plastic, BGA
IBM25PPC405GP3DE200CZ 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|456PIN|PLASTIC
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