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| 型號： | IBM25NPE405L-3FA133CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerNP |
| 中文描述： | 32-BIT, 133 MHz, RISC PROCESSOR, PBGA324 |
| 封裝： | 23 X 23 MM, PLASTIC, EBGA-324 |
| 文件頁數(shù)： | 35/54頁 |
| 文件大小： | 460K |
| 代理商： | IBM25NPE405L-3FA133CZ |
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
33
PHY0Col[PHY0Rx1Er]l
Collision [receive error] signal from the PHY. This is an
asynchronous signal (MII 0).
or
Receive Error ([RMII 1]).
I
5V tolerant
3.3V LVTTL
PHY0CrS[PHY0CrS0DV]
Carrier Sense signal from the PHY. This is an
asynchronous signal (MII 0).
or
Carrier sense data valid ([RMII 0]).
I
5V tolerant
3.3V LVTTL
1, 5
PHY0RxClk
Receiver medium clock. This signal is generated by the
PHY (MII 0).
I
5V tolerant
3.3V LVTTL
1, 4
PHY0RxD0[PHY0Rx0D0][PHY0Rx0D]
PHY0RxD1[PHY0Rx0D1][PHY0Rx1D]
PHY0RxD2[PHY0Rx1D0]
PHY0RxD3[PHY0Rx1D1]
Received Data. This is a nibble wide bus from the PHY.
The data is synchronous with PHY0RxClk
(MII 0[RMII 0, 1][SMII 0, 1]).
I
5V tolerant
3.3V LVTTL
1, 4
PHY0RxDV[PHY0CrS1DV]
Receive Data Valid. Data on the Data Bus is valid when
this signal is activated. Deassertion of this signal indicates
end of the frame reception (MII 0).
or
Carrier sense data valid ([RMII 1])
I
5V tolerant
3.3V LVTTL
1, 5
PHY0RxErr[PHY0Rx0Er]
Receive Error. This signal comes from the PHY and is
synchronous with PHY0RxClk (MII 0 [RMII 0]).
I
5V tolerant
3.3V LVTTL
1, 5
PHY0TxClk[PHY0RefClk]
Transmit medium clock. This signal is generated the PHY
([MII 0]).
or
Reference Clock [RMII and SMII].
I
5V tolerant
3.3V LVTTL
1, 4
SDRAM Interface
MemAddr00:31
Memory Data bus
Notes:
1. MemAddr00 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
I/O
3.3V LVTTL
MemAddr12:00
Memory Address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr00 is the least significant bit (lsb).
O
3.3V LVTTL
BA1:0
Bank Address supporting up to 4 internal banks
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM0:3
DQM for byte lane 0 (MemAddr00:7),
1 (MemAddr08:15),
2 (MemData16:23), and
3 (MemData24:31)
O
3.3V LVTTL
DQMCB
DQM for ECC check bits.
O
3.3V LVTTL
Signal Functional Description
(Part 2 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.
Signal Name
Description
I/O
Type
Notes
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IBM25NPE405L-3FA200C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA200CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA266C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA266CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25PPC403GAJC33C1 | 制造商:IBM 功能描述: |
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