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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
38
Notes:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, T
C
, is measured at top center of case surface with device soldered to circuit board.
b. T
A
= T
C
– P
×θ
CA
, where T
A
is ambient temperature and P is power consumption.
c. T
CMax
= T
JMax
– P
×θ
JC
, where T
JMax
is maximum junction temperature and P is power consumption.
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to the device.
Characteristic
Symbol
Value
Unit
Supply Voltage (Internal Logic)
V
DD
0 to +2.7
V
Supply Voltage (I/O Interface)
OV
DD
0 to +3.6
V
PLL Supply Voltage
2
AV
DD
0 to +2.7
V
Input Voltage (3.3V LVTTL receivers)
V
IN
-0.6 to (OV
DD
+ 0.6)
V
Input Voltage (5.0V LVTTL receivers)
V
IN
-0.6 to (OV
DD
+ 2.4)
V
Storage Temperature Range
T
STG
-55 to +150
°
C
Case temperature under bias
T
C
-40 to +120
°
C
Notes:
1. All voltages are specified with respect to ground (GND).
2. AV
DD
should be derived from V
DD
using the following circuit:
Package Thermal Specifications
The NPe405L is designed to operate within a case temperature range of -40°C to 85°C. Thermal resistance values for the
E-PBGA packages in a convection environment are as follows:
Package—Thermal Resistance
Symbol
Airflow
ft/min (m/sec)
Unit
0 (0)
100 (0.51)
200 (1.02)
23mm, 324-balls—Junction-to-Case
θ
JC
θ
CA
2
2
2
°C/W
23mm, 324-balls—Case-to-Ambient
1
17
15
14
°C/W
V
DD
C1
C2
C3
AV
DD
L1
L1 – 2.2
μ
H SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
C1 – 3.3
μ
F SMT tantalum
C2 –
0.1
μ
F SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
C3 – 0.01
μ
F SMT monolithic ceramic capacitor with X7R
dielectric or equivalent