參數(shù)資料
型號: IBM25EMPPC740LEBB4000
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255
封裝: 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255
文件頁數(shù): 15/50頁
文件大小: 600K
代理商: IBM25EMPPC740LEBB4000
Page 18
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
5/20/99
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
L2 Bus Input AC Specications
The L2 bus input interface AC timing specifications are found in the following table. See Figure 7.
L2 Bus Input Interface AC Timing Specications
Num
Characteristic
Min
Max
Unit
Notes
29,30
L2SYNC_IN rise and fall time
1.0
ns
2,3
24
Data and parity input setup to L2SYNC_IN, 300, 333, 366
MHz processor sorts.
1.5
ns
1
24
Data and parity input setup to L2SYNC_IN, 400 MHz pro-
cessor sort.
1.4
ns
1
24
Data and parity input setup to L2SYNC_IN, 466 MHz pro-
cessor sort.
1.1
ns
1
25
L2SYNC_IN to data and parity input hold
0.5
ns
1
Note:
1. All input specifications are measured from the midpoint voltage (1.4V) of the signal in question to the midpoint voltage of the rising edge of the input
L2SYNC_IN. Input timings are measured at the pins (see Figure 7).
2. Rise and fall times for the L2SYNC_IN input are measured from 0.4 to 2.4V.
3. Guaranteed by design and characterization, and not tested.
Figure 7. L2 Bus Input Timing Diagrams
VM
VM = Midpoint Voltage (1.4V)
L2SYNC_IN
25
24
ALL INPUTS
29
30
VM
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