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參數(shù)資料
| 型號： | IBM13T8644HPE |
| 廠商： | IBM Microeletronics |
| 英文描述： | One Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 8M x 64 PC100小外形雙列直插式同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 一位銀行8米× 64 SDRAM的內(nèi)存蘇（小外形雙列直插內(nèi)存模塊）（1組8米× 64 PC100的小外形雙列直插式同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 281K |
| 代理商： | IBM13T8644HPE |
IBM13T8644HPD
IBM13T8644HPE
One Bank 8M x 64 SDRAM SO DIMM
45L7125.E93903A
5/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 18
Clock Frequency and Latency
Symbol
Parameter
-10
Units
f
CK
Clock Frequency
100
66
MHz
t
CK
Clock Cycle Time
10
15
ns
t
AA
CAS Latency
3
2
CLK
t
RP
Precharge Time
3
2
CLK
t
RCD
RAS to CAS Delay
3
2
CLK
t
RC
Bank Cycle Time
9
6
CLK
t
RAS
Minimum Bank Active Time
6
4
CLK
t
DPL
Data In to Precharge
2
1
CLK
t
DAL
Data In to Active/Refresh
4
3
CLK
t
RRD
Bank to Bank Delay Time
2
2
CLK
t
CCD
CAS to CAS Delay Time
1
1
CLK
t
WL
Write Latency
0
0
CLK
t
DQW
DQM Write Mask Latency
0
0
CLK
t
DQZ
DQM Data Disable Latency
2
2
CLK
t
CSL
Clock Suspend Latency
1
1
CLK
Presence Detect Read and Write Cycle
Symbol
Parameter
Min
Max
Unit
Notes
f
SCL
SCL Clock Frequency
100
kHz
T
I
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
μ
s
t
HD:STA
Start Condition Hold Time
4.0
μ
s
t
LOW
Clock Low Period
4.7
μ
s
t
HIGH
Clock High Period
4.0
μ
s
t
SU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
μ
s
t
HD:DAT
Data in Hold Time
0
μ
s
t
SU:DAT
Data in Setup Time
250
ns
t
r
SDA and SCL Rise Time
1
μ
s
t
f
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
μ
s
t
DH
Data Out Hold Time
300
ns
t
WR
Write Cycle Time
15
ms
1
1. The Write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program
cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resis-
tor, and the device does not respond to its slave address.
Discontinued (4/1/00 last order; 7/31/00 - last ship)
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