參數(shù)資料
型號(hào)： IBM13T4644MPC
廠商： IBM Microeletronics
英文描述： 4M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(4M x 64小外形雙列直插同步動(dòng)態(tài)RAM模塊)
中文描述： 4米× 64 SDRAM的內(nèi)存蘇（小外形雙列直插內(nèi)存模塊）（4米× 64小外形雙列直插同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 5/14頁(yè)
文件大?。?/td> 273K
代理商： IBM13T4644MPC
IBM13T4644MPC
4M x 64 SDRAM SO DIMM
29L6293.E93850A
3/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 14
Serial Presence Detect
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
80
08
04
0C
08
01
4000
01
A0
70
00
80
10
00
01
8F
04
06
01
01
00
Notes
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at CL=3
SDRAM Device Access Time from Clock at CL=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attr: Min Clk Delay, Random Col Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latencies Supported
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
128
256
SDRAM
12
8
1
x64
LVTTL
10.0ns
7.0ns
Non-Parity
SR/1x(15.625
μ
s)
x16
N/A
1 Clock
1,2,4,8, Full Page
4
2, 3
0
0
Unbuffered
Wr-1/Rd Burst, Precharge All,
Auto-Precharge,
V
DD
±
10
%
15.0ns
8.0ns
N/A
N/A
6 - 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SDRAM Device Attributes: General
0E
23
24
25
26
Minimum Clock Cycle at CL
=
2
Maximum Data Access Time (t
AC
) from Clock at CL
=
2
Minimum Clock Cycle Time at CL
=
1
Maximum Data Access Time (t
AC
) from Clock at CL
=
1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Setup Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
Checksum for bytes 0 - 62
Manufacturers’ JEDEC ID Code
F0
80
00
00
1E
14
1E
3C
08
30
10
30
10
00
02
cc
27
30ns
28
20ns
29
30ns
30
31
32
33
34
35
60ns
32MB
3.0
1.0
3.0
1.0
Undefined
02
Checksum Data
IBM
Toronto, Canada
Vimercate, Italy
36 - 61
62
63
64 - 71
1
A400000000000000
91
53
313354343634344D50
rr2D31305420202020
rr20
72
Module Manufacturing Location
73 - 90
Module Part Number
ASCII ‘13T4644MP”R”-10T’
2, 3
91 - 92
Module Revision Code
“R” plus ASCII blank
2, 3
1. cc
=
Checksum Data byte, 00-FF (Hex)
2. “R”
=
Alphanumeric revision code, A-Z, 0-9
3. rr
=
ASCII coded revision code byte “R”
4. yy
=
Binary coded decimal year code, 00-99 (Decimal)
‘
00-63 (Hex)
5. ww
=
Binary coded decimal week code, 01-52 (Decimal)
‘
01-34 (Hex)
6. ss
=
Serial number data byte, 00-FF (Hex)
Discontinued (8/99 - last order; 12/99 - last ship)
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