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參數(shù)資料
| 型號： | IBM13T1649NC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 1M x 64 SDRAM SO DIMM(1M x 64 同步動態(tài)RAM模塊) |
| 中文描述： | 100萬蘇× 64 SDRAM的內存（100萬× 64同步動態(tài)內存模塊） |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 291K |
| 代理商： | IBM13T1649NC |
IBM13T4644MC
IBM13T1649NC
1M x 64 SDRAM SO DIMM
75H5936
GA14-4477-03
Rev 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 15
Common Parameters
Symbol
Parameter
-10
Units
Min.
Max.
t
CS
Command Setup Time
3
—
ns
t
CH
Command Hold Time
1
—
ns
t
AS
Address and Bank Select Set-up Time
3
—
ns
t
AH
Address and Bank Select Hold Time
1
—
ns
t
RCD
RAS to CAS Delay
30
—
ns
t
RC
Bank Cycle Time
90
120000
ns
t
RAS
Active Command Period
60
120000
ns
t
RP
Precharge Time
30
—
ns
t
RRD
Bank to Bank Delay Time
20
—
ns
t
CCD
CAS to CAS Delay Time (Same Bank)
1
—
CLK
Refresh Cycle
Symbol
Parameter
-10
Units
Notes
Min.
Max.
t
SREX
Self Refresh Exit Time
10ns + t
RC
—
ns
3
t
REF
Refresh Period
—
64
ms
1, 2
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-
up” the device.
3. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is
not complete until a time period equal to t
RC
is satisfied once the Self Refresh Exit command is registered.
Read Cycle
Symbol
Parameter
-10
Units
Notes
Min.
Max.
t
OH
Data Out Hold Time
3
—
ns
t
LZ
Data Out to Low Impedance Time
3
—
ns
t
HZ3
Data Out to High Impedance Time, CL= 3
3
8
ns
1
t
HZ2
Data Out to High Impedance Time, CL= 2
3
10
ns
1
t
HZ1
Data Out to High Impedance Time, CL= 1
3
18
ns
1
t
DQZ
DQM Data Out Disable Latency
2
—
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Discontinued (12/98 - last order; 9/99 last ship)
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