參數(shù)資料
型號(hào)： IBM13N16734HCB
廠(chǎng)商： IBM Microeletronics
英文描述： 16M x 72 Two-Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動(dòng)態(tài)RAM模塊)
中文描述： 1,600 × 72雙行緩沖內(nèi)存模組（16米x 72 2組不帶緩沖同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 10/18頁(yè)
文件大?。?/td> 331K
代理商： IBM13N16734HCB
IBM13N16644HCB
IBM13N16734HCB
16M x 64/72 Two-Bank Unbuffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 18
09K3605.F38386
12/99
Operating, Standby, and Refresh Currents
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Organization
Units
Notes
-x64
x72
Operating Current
t
=
t
(min), t
= min
Active-Precharge command cycling
without Burst operation
I
CC1
1 bank operation
t
=
t
(min), t
= min
Active-Precharge command
cycling without Burst operation
920
1035
mA
1, 3, 4
Precharge Standby Current in Power
Down Mode
I
CC2P
CKE0, CKE1
≤
V
IL
(max), t
CK
=
min,
S0 - S3 =V
IH
(min)
CKE0, CKE1
≤
V
IL
(max), t
CK
=
Infinity,
S0 - S3 =V
IH
(min)
CKE0, CKE1
≥
V
IH
(min), t
CK
=
min,
S0 - S3 =V
IH
(min)
CKE0, CKE1
≥
V
IH
(min), t
CK
=
Infinity,
S0 - S3 =V
IH
(min)
CKE0, CKE1
≥
V
IH
(min), t
CK
=
min,
S0 - S3 =V
IH
(min)
CKE0, CKE1
≤
V
IL
(max), t
CK
=
min,
S0 - S3 =V
(min)
(Power Down Mode)
16
18
mA
2
I
CC2PS
16
18
mA
2
Precharge Standby Current in Non-
Power Down Mode
I
CC2N
560
630
mA
2, 5
I
CC2NS
96
108
mA
2, 6
No Operating Current
(Active state: 4 bank)
I
CC3N
640
720
mA
2, 5
I
CC3P
48
54
mA
2, 7
Burst Operating Current
I
CC4
t
= min,
Read/ Write command cycling,
multiple banks active,
gapless data, BL = 4
1280
1440
mA
1, 4, 8
Auto (CBR) Refresh Current
I
CC5
t
= min,
CBR command cycling
1480
1665
mA
1
Self Refresh Current
I
CC6
I
SB
CKE0, CKE1
≤
0.2V
16
18
mA
2
Serial PD Device Standby Current
V
IN
= GND or V
DD
30
30
μ
A
9
Serial PD Device Active Power Sup-
ply Current
I
CCA
SCL Clock Frequency = 100KHz
1
1
mA
10
1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (I
CC3N
).
2. The specified values are for both DIMM banks operating in the specified mode.
3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
.
Input signals are changed up to three times during t
RC
(min).
4. The specified values are obtained with the output open.
5. Input signals are changed once during three clock cycles.
6. Input signals are stable.
7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ).
8. Input signals are changed once during t
CK(min)
.
9. V
DD
= 3.3V.
10. As follows:
Input pulse levels V
DD
x 0.1 to V
DD
x 0.9
Input rise and fall times 10ns
Input and output timing levels V
DD
x 0.5
Output load 1 TTL gate and CL=100pf
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