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參數(shù)資料
| 型號： | IBM13M32734BCB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2-Bank Registered SDRAM Module(32M x 72 2組寄存同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2，銀行注冊內(nèi)存模塊（32M × 72配置2組寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 575K |
| 代理商： | IBM13M32734BCB |
IBM13M32734BCB
32M x 72 2-Bank Registered SDRAM Module
19L7299.F38444A
8/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 20
Wiring and Topology
This section contains the information needed to understand the timing relationships presented in AC Charac-
teristics beginning on page 11. Each timing parameter is measured at the first receiving device (SDRAM DQ
pin for data, register input pin for address and control, and PLL Clk input pin for clock). This section will
enable the user to understand the pin numbers on the DIMM, the net structures, and the loading associated
with these devices. For detailed timing analysis, contact the IBM Marketing Representative for simulation
models. Modeling is strongly recommended to determine delay adders of the entire net structure.
Pin Assignments for the 64Mb SDRAM 2 High Stack Package (Dual CS Pin)
(Top View)
54-pin Plastic TSOJ(II) 400 mil
(4Mbit x 4 I/O x 4 Bank) x 2High
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
NC
V
DDQ
NC
DQ0
V
SSQ
NC
NC
V
DDQ
NC
DQ1
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS0/NC
A13/BS0
A12/BS1
A10/AP
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
NC
NC
V
SSQ
NC
DQ2
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC/CS1
A11
A9
A8
A7
A6
A5
A4
V
SS
A0
A1
A2
A3
V
DD
*
CS0 selects the lower DRAM in the stack.
*
CS1 selects the upper DRAM in the stack.
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