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參數(shù)資料
| 型號： | IBM13M32734BCB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2-Bank Registered SDRAM Module(32M x 72 2組寄存同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2，銀行注冊內(nèi)存模塊（32M × 72配置2組寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 575K |
| 代理商： | IBM13M32734BCB |
IBM13M32734BCB
32M x 72 2-Bank Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 20
19L7299.F38444A
8/99
Read Cycle
Symbol
Parameter
-75A
Units
Notes
Min.
Max.
t
OH
t
LZ
t
HZ3
t
DQZ
Data Out Hold Time
2.45
ns
Data Out to Low Impedance Time
0.6
ns
Data Out to High Impedance Time
3.6
6.6
ns
1
DQM Data Out Disable Latency
3
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-75A
Units
Min.
Max.
t
DS
t
DH
t
DPL
t
DAL3
t
DQW
Data In Setup Time
1.75
ns
Data In Hold Time
1.05
ns
Data input to Precharge
15
ns
Data in to Active Delay (CAS Latency = 3)
5
CLK
DQM Write Mask Latency
1
CLK
Presence Detect Read and Write Cycle
Symbol
f
SCL
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
DH
t
WR
Parameter
Min.
Max.
Units
Notes
SCL Clock Frequency
100
KHz
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
Time the Bus Must Be Free before a New Transmission Can Start
4.7
μ
s
Start Condition Hold Time
4.0
μ
s
Clock Low Period
4.7
μ
s
Clock High Period
4.0
μ
s
Start Condition Setup Time (for a Repeated Start Condition)
4.7
μ
s
Data in Hold Time
0
μ
s
Data in Setup Time
250
ns
SDA and SCL Rise Time
1
μ
s
SDA and SCL Fall Time
300
ns
Stop Condition Setup Time
4.7
μ
s
Data Out Hold Time
300
ns
Write Cycle Time
15
ms
1
1. The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
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