參數(shù)資料
型號(hào)： IBM13M32734BCA
廠商： IBM Microeletronics
英文描述： 32M x 72 2-Bank Registered SDRAM Module(32M x 72 2組寄存同步動(dòng)態(tài)RAM模塊)
中文描述： 32M × 72配置2，銀行注冊(cè)內(nèi)存模塊（32M × 72配置2組寄存同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 441K
代理商： IBM13M32734BCA
IBM13M32734BCA
32M x 72 2-Bank Registered SDRAM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 24
19L7297.F38442A
4/99
Serial Presence Detect
(Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD
Data Entry
(Hexadecimal)
Notes
0
Number of Serial PD Bytes Written during Produc-
tion
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Assembly Voltage Interface Levels
SDRAM Device Cycle Time (CL = 3)
SDRAM Device Access Time from Clock at CL=3
Assembly Error Detection/Correction Scheme
Assembly Refresh Rate/Type
SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attr: Min Clk Delay, Random Col
Access
SDRAM Device Attributes: Burst Lengths Sup-
ported
SDRAM Device Attributes: Number of Device
Banks
SDRAM Device Attributes: CAS Latency
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
128
80
1
2
3
4
5
256
08
04
0C
0A
02
4800
01
75
54
02
80
04
04
SDRAM
12
10
2
x72
LVTTL
7.5ns
5.4ns
ECC
6 - 7
8
9
10
11
12
13
14
1, 2
SR/1X(15.625
μ
s)
x4
x4
15
1 Clock
01
16
1, 2, 4, 8,Full Page
8F
17
4
04
18
19
20
21
3
0
0
04
01
01
IF
Registered/Buffered with PLL
Write-1/Read Burst, Precharge
All, Auto-Precharge
N/A
22
SDRAM Device Attributes: General
0E
23
Minimum Clock Cycle at CLX-1 (CL = 2)
Maximum Data Access Time (t
AC
) from Clock at
CLX-1 (CL = 2)
Minimum Clock Cycle Time at CLX-2 (CL = 1)
Maximum Data Access Time (t
AC
) from Clock at
CLX-2 (CL = 1)
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse width (t
RAS
)
Module Bank Density
00
1, 2
24
N/A
00
25
N/A
00
26
N/A
00
27
20.0ns
14
28
15ns
0F
29
20.0ns
14
30
31
45.0ns
128MB
2D
20
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock
cycles] + 1 = DIMM CAS latency).
2. Minimum application clock cycle time is 7.5ns (133MHz).
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-51 (Decimal) ‘ 01-34 (Hex).
7. yy = Binary coded decimal year code, 0-00 (Decimal) ‘ 00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
9. These values apply to PC100 applications only.
Discontinued (8/99 - last order; 12/99 - last ship)
相關(guān)PDF資料
PDF描述
IBM13M32734BCB 32M x 72 2-Bank Registered SDRAM Module(32M x 72 2組寄存同步動(dòng)態(tài)RAM模塊)
IBM13M32734BCC 32M x 72 2 Bank Registered SDRAM Module(32M x 72 2組寄存同步動(dòng)態(tài)RAM模塊)
IBM13M32734BCD 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
IBM13M32734BCE 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
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