
IBM11N4845BB
IBM11N4845CB
Preliminary
4M x 72 Chip-Kill Protect ECC-on-DIMM Module
75H5485
GA14-4640-00
Revised 11/96
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 29
Features
168 Pin JEDEC Standard, Unbuffered 8 Byte Dual
In-line Memory Module
4Mx72 Extended Data Out Page Mode DIMM
S
Performance:
All inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V
±
0.15V Power Supply
Optimized for ECC applications
Provides Chip-Kill (ECC) protection transparently to
an existing Single Error Correction (SEC) system
System Performance Benefits:
-Non buffered for increased performance
-Reduced noise (35 VSS/VCC pins)
-Serial PDs
Extended Data Out (EDO) Mode, Read-Modify-Write
Cycles
Refresh Modes: RAS-Only, CBR and Hidden Refresh
2048 refresh cycles distributed across 32ms (11/11
addressing)
4096 refresh cycles distributed across 64ms (12/10
addressing)
11/11 or 12/10 addressing (Row/Column)
Card size: 5.25" x 1.2" x 0.354"
DRAMS in SOJ Package
Au contacts
Description
The IBM11N4845BB and IBM11N4845CB are industry
standard 168-pin 8-byte Dual In-line Memory Modules
(DIMMs) which are organized as a 4Mx72 high speed
memory array supporting EDO applications. The DIMM
uses 18 4Mx4 EDO DRAMs in SOJ packages along with
an ASIC and check bit DRAMs to provide an SEC ECC
system with transparent chip kill protection.
The DIMMs use serial presence detects implemented via
a serial EEPROM using the two pin I
2
C protocol. This
communication protocol uses Clock (SCL) and Data I/O
(SDA) lines to synchronously clock data between the
master (system logic) and the slave EEPROM device
(DIMM). The EEPROM device address pins (SA0-2) are
brought out to the DIMM tabs to allow 8 unique
DIMM/EEPROM addresses. The first 128 bytes are uti-
lized by the DIMM manufacturer and the second 128
bytes of serial PD data are available to the customer.
All IBM 168-pin DIMMs provide a high performance, flexi-
ble 8-byte interface in a 5.25” long space-saving footprint.
Related products include the buffered DIMMs (x64, x72
parity and x72 ECC Optmized) for applications which can
benefit from the on-card buffers.
-6R
60ns
18ns
30ns
104ns
25ns
t
RAC
t
CAC
t
AA
t
RC
t
HPC
RAS Access Time
CAS Access Time
Access Time From Address
Cycle Time
EDO Mode Cycle Time
Card Outline
1
85
10
94
11
95
40
124
41
125
84
168
(Front)
(Back)
IBM11M4730C4M x 72 E12/10, 5.0V, Au.