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| 型號： | IBM11N16845BB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 72 Chip-Kill Protect ECC-on-DIMM Module(16M x 72 帶糾錯代碼保護(hù)的小外形雙列直插動態(tài)RAM模塊) |
| 中文描述： | 1,600 × 72片，殺死保護(hù)ECC的上內(nèi)存模塊（1,600 × 72帶糾錯代碼保護(hù)的小外形雙列直插動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 7/29頁 |
| 文件大?。?/td> | 502K |
| 代理商： | IBM11N16845BB |
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IBM11N16845BB
IBM11N16845CB
Preliminary
16M x 72 Chip-Kill Protect ECC-on-DIMM Module
75H5487
GA14-4642-00
Revised 11/96
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 29
AC Characteristics
(T
C
= 0 to +60
°
C, V
CC
=
3.3V
±
0.15V)
1. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Transition times are measured between V
IH
and
V
IL
.
2. An initial pause of 200ms is required after power-up followed by 8 RAS only refresh cycles before proper device and ASIC operation
is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required..
3. AC measurements assume t
T
= 2ns.
.
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Parameter
-6R
Unit
Notes
Min
Max
t
RC
Random Read or Write Cycle Time
104
—
ns
t
RP
RAS Precharge Time
40
—
ns
t
CP
CAS Precharge Time
10
—
ns
t
RAS
RAS Pulse Width
60
100K
ns
t
CAS
CAS Pulse Width
10
100K
ns
t
ASR
Row Address Setup Time
0
—
ns
t
RAH
Row Address Hold Time
10
—
ns
t
ASC
Column Address Setup Time
0
—
ns
t
CAH
Column Address Hold Time
10
—
ns
t
RCD
RAS to CAS Delay Time
14
42
ns
1
t
RAD
RAS to Column Address Delay Time
12
30
ns
2
t
RSH
RAS Hold Time
10
—
ns
t
CSH
CAS Hold Time
50
—
ns
t
CRP
CAS to RAS Precharge Time
5
—
ns
t
ODD
OE to D
IN
Delay Time
15
—
ns
3
t
DZO
OE Delay Time from D
IN
0
—
ns
4
t
DZC
CAS Delay Time from D
IN
0
—
ns
4
t
T
Transition Time (Rise and Fall)
2
30
ns
1. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. The t
RCD
(max) is specified as a reference point only: If t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled by t
CAC.
2. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. The t
RAD
(max) is specified as a reference point only: If t
RAD
is greater than the specified t
RAD
(max) limit, then access time is controlled by t
AA.
3. Either t
CDD
or t
ODD
must be satisfied.
4. Either t
DZC
or t
DZO
must be satisfied.
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