參數(shù)資料
型號(hào)： IBM11M4735C
廠商： IBM Microeletronics
英文描述： 4M x 72 DRAM Module(4M x 72動(dòng)態(tài)RAM模塊)
中文描述： 4米× 72內(nèi)存（4米× 72動(dòng)態(tài)內(nèi)存模塊）
文件頁數(shù)： 1/30頁
文件大小： 791K
代理商： IBM11M4735C
IBM11M4735C
IBM11M4735CB
4M x 72 DRAM Module
50H4201.E20982E
Revised 8/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 30
Features
168-Pin JEDEC-Standard 8-Byte Dual In-Line
Memory Module
4Mx72 Extended Data Out Page Mode DIMM
Performance:
Inputs and outputs are LVTTL (3.3V) or TTL
(5.0V) compatible
Single 3.3V
±
0.3V or 5.0V
±
0.5V Power Supply
Gold contacts
Optimized for ECC applications
System Performance Benefits:
- Buffered inputs (except RAS, Data)
- Reduced noise (32 V
SS
/V
CC
pins)
- 4-Byte Interleave enabled
- Buffered PDs
Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
Refresh Modes: RAS-Only, CBR and Hidden
Refresh
4096 refresh cycles distributed across 64ms
12/10 addressing (Row/Column)
Card sizes: 5.25" x 1.0" x 0.354" (SOJ)
5.25" x 1.0" x 0.175" (TSOP)
DRAM
S
in SOJ or TSOP Package
Description
IBM11M4735C is an industry-standard 168-pin
8-byte Dual In-Line Memory Module (DIMM) which
is organized as a 4Mx72 high-speed memory array
designed with EDO DRAMs for ECC applications.
The DIMM uses 18 4Mx4 EDO DRAMs in SOJ or
TSOP packages. The use of EDO DRAMs allows for
a reduction in Page Mode Cycle time from 40ns
(Fast Page) to 20ns for 50ns DRAM modules.
Improved system performance is provided by the
on-DIMM buffering of selected input signals. The
specified timings include all buffer, net and skew
delays, which simplifies the memory subsystem
design analysis. The data and
RAS
signals are not
buffered, which preserves the DRAM access specifi-
cations of 50ns and 60ns.
Presence Detect (PD) and Identification Detect (ID)
bits provide information about the DIMM density,
addressing, performance, and features. PD bits can
be dotted at the system level and activated for each
DIMM position using the PD enable (PDE) signal. ID
bits also allow detection of card features, and may
be dot-or’d at the system level to provide information
for the entire DIMM bank. For example, the system
will determine that ECC DIMMs are installed if PD8
is low (0). ID0 need not be sensed since both x72
and x80 ECC DIMMs will function in a x72 bank.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products are the x64 non-parity
DIMMs and the ECC DIMMs (5V and 3.3V).
Card Outline 3.3V
-50
-60
t
RAC
RAS Access Time
50ns
60ns
t
CAC
CAS Access Time
18ns
20ns
t
AA
Access Time From Address
30ns
35ns
t
RC
Cycle Time
89ns
104ns
t
HPC
EDO Mode Cycle Time
20ns
25ns
1
85
10
94
11
95
40
124
41
125
84
168
(Front)
(Back)
See Detail A
for 5.0V Version
Detail A
IBM11M4730C4M x 72 E12/10, 5.0V, Au.
Discontinued (9/98 - last order; 3/99 - last ship)
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