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參數(shù)資料
| 型號： | IBM11M4730CF |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) |
| 中文描述： | 4米× 72內(nèi)存（4米× 72動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 500K |
| 代理商： | IBM11M4730CF |
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IBM11M4730CB
IBM11M4730CF
4M x 72 DRAM Module
IBM11M4730CH
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 27
64G1557.E20999D
Revised 4/98
Write Cycle
Symbol
Parameter
-60
Unit
Notes
Min
Max
t
WCS
Write Command Set Up Time
2
—
ns
1
t
WCH
Write Command Hold Time
17
—
ns
t
WP
Write Command Pulse Width
15
—
ns
t
RWL
Write Command to RAS Lead Time
20
—
ns
t
CWL
Write Command to CAS Lead Time
17
—
ns
t
WCR
Write Command Hold Time Referenced to RAS
—
—
ns
2
t
DHR
Data Hold Time Referenced to RAS
—
—
ns
2
t
DS
D
IN
Setup Time
-2
—
ns
3
t
DH
D
IN
Hold Time
17
—
ns
3
1. t
WCS
, t
RWD
, t
CWD
, t
AWD
, and t
CPW
are not restrictive parameters. They are included in the data sheet as electrical characteristics only.
If t
WCS
≥
t
WCS
(min.), the entire cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the
entire cycle. If t
RWD
≥
t
RWD
(min.), t
CWD
≥
t
CWD
(min.), t
AWD
≥
t
AWD
(min.), and t
CPW
≥
t
CPW
(min.)(Fast Page Mode), the cycle is a Read-
Modify-Write cycle and the data will contain read from the selected cell: If neither of the above sets of conditions is met, the condi-
tion of the data (at access time) is indeterminate.
2. This timing parameter is not applicable to this product, but applies to a related product in this family.
3. Data-in setup and hold is measured from the latter of the two timings, CAS or WE.
Discontinued (9/98 - last order; 3/99 last ship)
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