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參數(shù)資料
| 型號： | IBM11M2730HB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 2M x 72 DRAM Module(2M x 72 動態(tài)RAM模塊) |
| 中文描述： | 200萬× 72內(nèi)存（2米× 72動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 502K |
| 代理商： | IBM11M2730HB |
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IBM11M2730H
IBM11M2730HB
2M x 72 DRAM MODULE
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 26
64G1556
SA14-4610-03
Revised 5/96
Truth Table
Function
RAS
CAS
WE
OE
Row
Address
Column
Address
PDE
DQx
Standby
Read
Early-Write
H
L
L
H
→
X
L
L
X
H
L
X
L
X
X
X
X
X
X
High Impedance
Valid Data Out
Valid Data In
Valid Data Out,
Valid Data In
Row
Row
Col
Col
Late-Write / RMW
L
L
H
→
L
L
→
H
Row
Col
X
Fast Page Mode - Read
1st Cycle
Subsequent Cycles
Fast Page Mode - Write
1st Cycle
Subsequent Cycles
Fast Page Mode - RMW
1st Cycle
L
H
→
L
H
L
Row
Col
X
Valid Data Out
L
H
→
L
H
L
N/A
Col
X
Valid Data Out
L
H
→
L
L
X
Row
Col
X
Valid Data In
L
H
→
L
L
X
N/A
Col
X
Valid Data In
L
H
→
L
H
→
L
L
→
H
Row
Col
X
Valid Data Out,
Valid Data In
Subsequent Cycles
L
H
→
L
H
→
L
L
→
H
N/A
Col
X
Valid Data Out,
Valid Data In
RAS-Only Refresh
L
H
X
X
Row
N/A
X
High Impedance
CAS-Before-RAS Refresh
H
→
L
L
H
X
X
X
X
High Impedance
Hidden Refresh
Read
L
→
H
→
L
L
H
L
Row
Col
X
Data Out
Write
L
→
H
→
L
L
H
X
Row
Col
X
Data In
Read Presence Detects
X
X
X
X
X
X
L
Not Affected
(PD Bits Valid)
Presence Detect
Pin
-60
-70
PD1 (PD1 - PD4: Addressing/Density)
1
1
PD2
0
0
PD3
0
0
PD4
1
1
PD5 (EDO Detection)
0
0
PD6 (PD6 - PD7: Speed)
1
0
PD7
1
1
PD8 (Parity/ECC Designator)
0
0
ID0 (DIMM Type/Width)
0
0
ID1 (Refresh Mode)
0
0
1. PD1-8 are buffered outputs (0 = driven to V
OL
, 1 = open)
2. ID0-1 are unbuffered outputs (0 = V
SS
, 1 = open)
3. PDE should be tied high or low at system level if not used
Discontinued (9/98 - last order; 3/99 last ship)
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