- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378600 > IBM0364404 (IBM Microeletronics) 64Mb(4Mbit x 4 I/O x 4 Bank) Synchronous DRAM(64M位(4M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | IBM0364404 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64Mb(4Mbit x 4 I/O x 4 Bank) Synchronous DRAM(64M位(4M位 x 4 I/O x 4 組)同步動(dòng)態(tài)RAM) |
| 中文描述： | 64兆（的4Mb × 4的I / O × 4行）同步DRAM（6400位（4分位× 4的I / O × 4組）同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 1/72頁 |
| 文件大?。?/td> | 1201K |
| 代理商： | IBM0364404 |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
19L3264.E35855A
1/28/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 72
Features
High Performance:
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
Four Banks controlled by A12/A13 (Bank
Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8, full-page
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4, x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard or Low Power operation
4096 refresh cycles/64ms
Random Column Address every CLK (1-N Rule)
Single 3.3V
±
0.3V Power Supply
LVTTL compatible
Package: 54-pin 400 mil TSOP-Type II
2 High Stack TSOJ
Description
The IBM0364404, IBM0364804, and IBM0364164
are four-bank Synchronous DRAMs organized as
4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and
1Mbit x 16 I/O x 4 Bank, respectively. IBM03644B4,
a stacked version of the x4 component, is also
offered. These synchronous devices achieve high-
speed data transfer rates of up to 147MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM’s advanced 64Mbit single tran-
sistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC
standards for synchronous DRAM products, both
electrically and mechanically. All the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CLK). Internal chip operating modes
are defined by combinations of these signals, and a
command decoder initiates the necessary timings
for each operation. A fourteen-bit address bus
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
and two bank select addresses (A12, A13) are
strobed with RAS. Ten column addresses (A0-A9)
plus bank select addresses and A10 are strobed
with CAS. Column address A9 is dropped on the x8
device and column addresses A8 and A9 are
dropped on the x16 device. Access to the lower or
upper DRAM in a stacked device is controlled by
CS0 and CS1, respectively.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A13
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 147MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Simultaneous oper-
ation of both decks of a stacked device is allowed,
depending on the operation being done.
Auto Refresh (CBR), Self Refresh, and Low Power
operation are supported.
-68,
CL=3
-260,
CL=3
-360,
CL=3
-10,
CL=3
Units
f
CK
Clock Frequency
147
135
135
100
MHz
t
CK
Clock Cycle
6.8
7.4
7.4
10
ns
t
AC
Clock Access Time
1
6
—
—
7
ns
t
AC
Clock Access Time
2
—
6
6
9
ns
1. Terminated load. See AC Characteristics on page 44.
2. Unterminated load. See AC Characteristics on page 44.
IBM036440416M x 412/10/2, 3.3V 72. IBM03644B432M x 412/10/2, 3.3V 72. IBM03641644M x 1612/8/2, 3.3V 72. IBM03648048M x 412/9/2, 3.3V 72.
Discontinued (8/99 - last order; 12/99 - last ship)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM03644B4 | 64Mb Synchronous DRAM(64M位同步動(dòng)態(tài)RAM) |
| IBM0364804 | 64Mb(2Mbit x 8 I/O x 4 Bank) Synchronous DRAM(64M位(2M位 x 8 I/O x 4 組)同步動(dòng)態(tài)RAM) |
| IBM043612PQKB | 32K X 36 BURST SRAM(1M (32K X 36)同步可猝發(fā)高性能靜態(tài)RAM) |
| IBM11D1320L | 1M x 32 DRAM Module(1M x 32 動(dòng)態(tài)RAM模塊) |
| IBM11D2320L | 2M x 32 DRAM Module(2M x 32 動(dòng)態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM0364404CT3A365 | 制造商:IBM 功能描述:* |
| IBM0364404CT3B260 | 制造商:IBM 功能描述:* |
| IBM0364404CT3B75A | 制造商:IBM 功能描述:* |
| IBM0364404CT3C260 | 制造商:IBM 功能描述:* |
| IBM0364404CT3C75A | 制造商:IBM 功能描述:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。