參數(shù)資料
型號： IBM0364164C
廠商： IBM Microeletronics
英文描述： 64Mb （1Mbit x 16 I/O x4 Bank）Synchronous DRAM(64M位（1M位 x 16 I/O x 4 組）同步動態(tài)RAM)
中文描述： 64兆（容量為1Mbit × 16的I / O x4銀行）同步DRAM（6400位（100萬位× 16的I / O × 4組）同步動態(tài)RAM）的
文件頁數(shù)： 1/69頁
文件大?。?/td> 1003K
代理商： IBM0364164C
IBM0364404C IBM0364164C
IBM0364804C IBM03644B4C
64Mb Synchronous DRAM - Die Revision A
03K2149
GA14-5286-09
3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 69
Features
High Performance:
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
Four Banks controlled by A12/A13 (Bank Select)
Programmable CAS Latency: 2,3
Programmable Burst Length: 2,4,8,full-page
-360,
CL=3
-365,
CL=3
-370,
CL=3
-10,
CL=3
Units
f
CK
Clock Frequency
100
100
100
100
MHz
t
CK
Clock Cycle
10
10
10
10
ns
t
AC
Clock Access Time
1
—
—
—
8
ns
t
AC
Clock Access Time
2
6
6.5
7
9
ns
Note:
1
Terminated load,
2
Unterminated load. See AC Characteristics (page 42).
Programmable Wrap Sequence: Sequential or
Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4,x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 refresh cycles/64ms
Random Column Address every CLK (1-N Rule)
Single 3.3V
±
0.3V Power Supply
LVTTL compatible
Package: 54 pin 400 mil TSOP-Type II
2 High Stack TSOJ
Description
The
IBM0364404C,
IBM0364804C,
and
IBM0364164C are four bank Synchronous DRAMs
organized as 4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x
4 Bank, and 1Mbit x 16 I/O x 4 Bank, respectively.
IBM03644B4C is a stacked version of the x 4 com-
ponent. These synchronous devices achieve high
speed data transfer rates of up to 100MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM’s advanced 64Mbit single tran-
sistor CMOS DRAM process technology.
The device is designed to comply with all
JEDEC standards set for synchronous DRAM prod-
ucts, both electrically and mechanically. All of the
control, address and data input/output (I/O or DQ)
circuits are synchronized with the positive edge of
an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals
which are examined at the positive edge of each
externally applied clock (CLK). Internal chip operat-
ing modes are defined by combinations of these sig-
nals and a command decoder initiates the
necessary timings for each operation. A fourteen
bit address bus accepts address data in the conven-
tional RAS/CAS multiplexing style. Twelve row
addresses (A0-A11) and two bank select addresses
(A12, A13) are strobed with RAS. Ten column
addresses (A0-A9) plus bank select addresses and
A10 are strobed with CAS. Column address A9 is
dropped on the x8 device and column addresses A8
and A9 are dropped on the x16 device. Access to
the lower or upper DRAM in a stacked device is con-
trolled by CS0 and CS1, respectively.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A9
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the four memory banks in an inter-
leave fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
100MHz is possible depending on burst length, CAS
latency, and speed grade of the device. Simulta-
neous operation of both decks of a stacked device is
allowed, depending on the operation being done.
Auto Refresh (CBR) and Self Refresh operation
are supported.
.
相關(guān)PDF資料
PDF描述
IBM0364404C 64Mb （4Mbit x 4 I/O x 4 Bank）Synchronous DRAM(64M位（4M位 x 4 I/O x 4 組）同步動態(tài)RAM)
IBM03644B4C 64Mb Synchronous DRAM(64M位同步動態(tài)RAM)
IBM0364804C 64Mb （2Mbit x 8 I/O x4 Bank）Synchronous DRAM(64M位（2M位 x 8 I/O x 4 組）同步動態(tài)RAM)
IBM0364164 64Mb(1Mbit x 16 I/O x 4 Bank) Synchronous DRAM(64M位(1M位 x 16 I/O x 4 組)同步動態(tài)RAM)
IBM0364404 64Mb(4Mbit x 4 I/O x 4 Bank) Synchronous DRAM(64M位(4M位 x 4 I/O x 4 組)同步動態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM0364164CT3B360 制造商:IBM 功能描述:*
IBM0364164PT3B360 制造商:IBM 功能描述:*
IBM0364164PT3C10 制造商:IBM 功能描述:*
IBM0364164PT3C360 制造商:IBM 功能描述:*
IBM0364404CT3A365 制造商:IBM 功能描述:*
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