參數(shù)資料
型號： IBM0312164
廠商： IBM Microeletronics
英文描述： 128Mb（2Mbit x 16 I/O x 4 Bank） Synchronous DRAM(128M位（2M位 x 16 I/O x 4 組）同步動態(tài)RAM)
中文描述： 128Mb的（2Mbit的× 16的I / O × 4行）同步DRAM（128兆位（200萬位× 16的I / O × 4組）同步動態(tài)RAM）的
文件頁數(shù)： 1/70頁
文件大小： 3145K
代理商： IBM0312164
IBM0312804 IBM0312164
IBM0312404 IBM03124B4
128Mb Synchronous DRAM - Die Revision A
33L8019.F45415
7/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 70
Features
High Performance:
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
Four Banks controlled by BS0/BS1 (bank select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8, full-page
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4, x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard or Low Power operation
4096 refresh cycles/64ms
Random Column Address every CLK (1-N Rule)
Single 3.3V
±
0.3V Power Supply
LVTTL compatible
Package: 54-pin 400 mil TSOP-Type II
2 High Stack TSOJ
Description
The IBM0312404, IBM0312804, and IBM0312164
are four-bank Synchronous DRAMs organized as
8Mbit x 4 I/O x 4 Bank, 4Mbit x 8 I/O x 4 Bank, and
2Mbit x 16 I/O x 4 Bank, respectively. IBM03124B4,
a stacked version of the x4 component, is also
offered. These synchronous devices achieve high-
speed data transfer rates of up to 133MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM’s advanced 128Mbit single tran-
sistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC
standards set for synchronous DRAM products,
both electrically and mechanically. All of the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CLK). Internal chip operating modes
are defined by combinations of these signals and a
command decoder initiates the necessary timings
for each operation. A fourteen bit address bus
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
and two bank select addresses (BS0, BS1) are
strobed with RAS. Eleven column addresses (A0-
A9, A11) plus bank select addresses and A10 are
strobed with CAS. Column address A11 is dropped
on the x8 device and column addresses A9 and A11
are dropped on the x16 device. Access to the lower
or upper DRAM in a stacked device is controlled by
CS0 and CS1, respectively.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A13
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 133MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Simultaneous opera-
tion of both decks of a stacked device is allowed,
depending on the operation being done. Auto
Refresh (CBR), Self Refresh, and Low Power opera-
tion are supported.
-75A,
CL=3
133
-260,
CL=2
100
-360,
CL=3
100
-10,
CL=3
100
Units
f
CK
Clock Frequency
t
CK
Clock Cycle
t
AC
Clock Access Time
1
t
AC
Clock Access Time
2
MHz
7.5
10
10
10
ns
—
—
—
7
ns
5.4
6
6
9
ns
1. Terminated load. See AC Characteristics on page 39.
2. Unterminated load. See AC Characteristics on page 39.
.
相關(guān)PDF資料
PDF描述
IBM0312404 128Mb（8Mbit x 4 I/O x 4 Bank） Synchronous DRAM(128M位（8M位 x 4 I/O x 4 組）同步動態(tài)RAM)
IBM03124B4 128Mb Synchronous DRAM(128M位同步動態(tài)RAM)
IBM0312804 128Mb（4Mbit x 8 I/O x 4 Bank） Synchronous DRAM(128M位（4M位 x 8 I/O x 4 組）同步動態(tài)RAM)
IBM0316169C 16Mb（512Kbit x 16 I/O x 2 Bank）Synchronous DRAM(16M位（512K位 x 16 I/O x 2 組）同步動態(tài)RAM)
IBM0316409C 16Mb（2Mbit x 4 I/O x 2 Bank）Synchronous DRAM(16M位（2M位 x 4 I/O x 2 組）同步動態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM0312164PT3A360 制造商:IBM 功能描述:*
IBM0312404CT3A260 制造商:IBM 功能描述:*
IBM0312804CT3A260 制造商:IBM 功能描述:*
IBM0312804CT3A360 制造商:IBM 功能描述:*
IBM0312804CT3A75A 制造商:IBM 功能描述:*
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