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參數(shù)資料
| 型號(hào)： | IA88C00-PLC68I-R-01 |
| 廠商： | Innovasic Semiconductor |
| 文件頁(yè)數(shù)： | 61/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 20MHZ 68PLCC |
| 標(biāo)準(zhǔn)包裝： | 285 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | EBI/EMI，UART/USART |
| 外圍設(shè)備： | DMA，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器類型： | 外部程序存儲(chǔ)器 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 管件 |
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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright 2005
ENG21 1 030617-04
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 64 of 80
1.888.824.4184
Once the complete character is assembled, the UART checks it and performs the following actions:
1. Sets the Control Character status bit, if it is an ASCII control character.
2. Checks the wake-up settings and completes any indicated action.
3. Checks to see if the calculated parity matches the programmed parity bit, if parity is enabled. If they
do not match, it sets the parity Error bit in URC (R236, Bank 0), which remains set until reset by
software.
4. Resets the Framing Error bit (URC, bit 4), if the character is assembled without any stop bits. This bit
remains set until cleared by software.
Overrun errors occur when characters are received faster than they are read. That is, when the UART has
assembled a complete character before the CPU has read current character, the UART sets the Overrun
Error bit (URC, bit 3), and the character currently in the receive buffer is lost.
The overrun bit remains set until cleared by software.
Address Space
The IA88C00 can access 64 Kbytes of program memory and 64 Kbytes of data memory. These spaces can
be either combined or separate. If separate, they are controlled by the DM line (Port P35), which selects
data memory when Low and program memory when High.
CPU Program Memory
Program memory occupies address 0 to 64K. External program memory is accessed by configuring Ports
0 and/or 1 and/or 4 as the memory interface.
The address/data lines are controlled by AS, DS and R/W.
The first 32 program memory bytes are reserved for interrupt vectors. The lowest address available for
user programs is 32 (decimal). This value is automatically loaded into the program counter after a
hardware reset. Port 0 can be configured to provide from 0 to 8 additional address lines. Port 1 is used as
an 8-bit multiplexed address/data port or as a data port when in de-mux mode.
CPU Data Memory
If separated from program memory by the DM optional output, the external CPU data memory space can
be mapped anywhere from 0 to 64K (full 16-bit address space). Data memory uses the same address/data
bit (Port 1) and additional address (chosen from Port 0) as program memory. The DM pin (P35) is mainly
what distinguishes data memory from program memory. It is also distinguished by the fact that data
memory can begin at address 0000H.
Figure 62 shows the system memory space.
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