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參數(shù)資料
| 型號(hào)： | IA88C00-PLC68I-R-01 |
| 廠商： | Innovasic Semiconductor |
| 文件頁(yè)數(shù)： | 13/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 20MHZ 68PLCC |
| 標(biāo)準(zhǔn)包裝： | 285 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | EBI/EMI，UART/USART |
| 外圍設(shè)備： | DMA，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器類型： | 外部程序存儲(chǔ)器 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 包裝： | 管件 |
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IA88C00
Data Sheet
Microcontroller
As of Production Version -01
Copyright 2005
ENG 21 0 050519-00
www.Innovasic
Innovasic.com
Innovasic Semiconductor
Page 20 of 80
1.888.824.4184
Mode and Control Registers
Figure 10. R213 (D5) Flags System Flags Register
Bit
7
6
5
4
3
2
1
0
Carry
Zero
Sign
Overflow
Decimal
Adjust
Half-
Carry
Fast
Interrupt
Bank
Initial Value
?
Read/Write
R
R/W
The flag register contains eight bits that describe the current status of the processor. Four of these bits can
be tested and used with conditional jump instructions. Two others are used for BCD arithmetic. Also
contained in the flag register are the Bank Address bit and the Fast Interrupt Status bit.
Bit 7: Carry Flag - This is set to 1 if the result from an arithmetic operation generates carry out of, or
borrow into, bit 7.
Bit 6: Zero Flag - For arithmetic and logical operations, this flag is set to 1 if the result of the operation is
0. For operations that test bits in a register, the 0 bit is set to 1 if the result is 0. For rotate and shift
operations, this bit is set to 1 if the result is 0.
Bit 5: Sign Flag - Following arithmetic, logical, rotate or shift operations, this bit identifies the state of
the MSB of the result. A 0 indicates a positive number and a 1 indicates a negative number.
Bit 4: Overflow Flag - This flag is set to 1 when the result of a two's-complement operation was greater
than 127 or less than -128. It is also cleared to 0 during logical operations.
Bit 3: Decimal Adjust - This bit is used to specify what type of instruction was executed last during BCD
operations, so a subsequent decimal adjust operation can function correctly. This bit is not usually
accessible to programmers and cannot be used as a test condition.
Bit 2: Half-Carry Flag - This bit is set to 1 whenever an addition generates a carry out of bit 3, or when a
subtraction borrows out of bit 4. This bit is used by the Decimal Adjust (DA) instruction to convert the
binary result of a previous addition or subtraction into the correct decimal (BCD) result. This flag and the
Decimal Adjust flag are not usually accessed by users.
Bit 1: Fast Interrupt Status - This bit is set during a fast interrupt cycle and reset during the IRET
following interrupt servicing. When set, this bit inhibits all interrupts and causes the fast interrupt return
to be executed when the IRET instruction is fetched.
Bit 0: Bank Address - This bit is used to select one of the register banks (0 or 1) between (decimal)
addresses 224 and 255. It is cleared by the SB0 instruction and set by the SB1 instruction.
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