參數(shù)資料
型號: IA82050-PDW28I-R-01
廠商: Innovasic Semiconductor
文件頁數(shù): 5/22頁
文件大?。?/td> 0K
描述: IC ASYNCHRONOUS SERIAL CTRL
標準包裝: 325
系列: *
IA82050
Data Sheet
Asynchronous Serial Controller
February 25, 2011
IA211030617-08
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 13 of 22
1-888-824-4184
Table 6. Modem Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
LC
OUT2
OUT1
RTS
DTR
LC
Loopback Control (0=normal operation, 1=loopback mode)
OUT2
Output 2 State (1=OUT2N low, 0=OUT2N high)
OUT1
Output 1 State (1=OUT1N low, 0=OUT1N high)
RTS
Ready To Send State (1=RTSN low, 0=RTSN high)
DTR
Data Terminal Ready State (1=DTRN low, 0=DTRN high)
4.7
Modem Status Register (MSR)
Reports status of modem input pins DCDN, RIN, DSRN and CTSN. All but CTSN must be
enabled via the PMD register. The “delta” bits are cleared on a read. (ADDR 110, Mode R/W;R,
Default 00000000).
Table 7. Modem Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DCDC
RIC
DSRC
CTSC
DDCD
DRI
DDSR
DCTS
DCDC
DCDN Complement (1=DCDN low, 0=DCDN high)
RIC
RIN Complement (1=RIN low, 0=RIN high)
DSRC
DSRN Complement (1=DSRN low, 0=DSRN high)
CTSC
CTSN Complement (1=CTSN low, 0=CTSN high)
DDCD
Delta DCDN (1=DCDN changed since last read, 0=no change)
DRI
Delta RIN (1=RIN transitioned low since last read, 0=no change or transition high)
DDSR
Delta DSRN (1=DSRN changed since last read, 0=no change)
DCTS
Delta CTSN (1=CTSN changed since last read, 0=no change)
4.8
Receive Data Register (RXDATA)
(ADDR 000, Mode R, Default Unknown)
Receive Data - A read from this location removes the data receive byte from the RX FIFO. The
LSB of RXDATA will correspond to the first bit received after the start bit of the serial
character. The MSB will correspond to the eighth data bit received after the start bit. If the
character length (LCR_CL) is less than eight, the unused RXDATA bits will be zero.
A read from RXDATA will be directly from the RX FIFO.
4.9
Scratch Register (SCR)
(ADDR 111, Mode R/W, Default 00000000)
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