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參數(shù)資料
| 型號： | IA82050-PDW28I-R-01 |
| 廠商： | Innovasic Semiconductor |
| 文件頁數(shù)： | 22/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ASYNCHRONOUS SERIAL CTRL |
| 標(biāo)準(zhǔn)包裝： | 325 |
| 系列： | * |
IA82050
Data Sheet
Asynchronous Serial Controller
February 25, 2011
IA211030617-08
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 9 of 22
1-888-824-4184
3.
Functional Overview
3.1
Transmitter
The Transmit function consists of a one-character FIFO, and a Transmit Engine. The transmit
engine is responsible for reading the data out of the FIFO and placing it in the proper order on
the TXD pin. The transmit engine is highly configurable to be compatible with numerous
formats, including 16450 and 8250 modes of communication. Transmit Communication
parameters that can be programmed include:
Parity modes
Stop Bits
Character Length
For more details, see Chapter 5, Register Descriptions.
3.2
Receiver
The Receiver function consists of a one-character FIFO and a receive engine. The receive
engine is responsible for sampling the data on the RXD input pin, formatting the data, and
placing the data in the FIFO. The receive engine is highly configurable with parameters that
include:
Parity modes
Stop Bits
Character Length
For more details, see Chapter 5, Register Descriptions.
3.3
Bus Interface
The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read
and write the IA82050 Registers. It consists of the following I/O lines:
A0, A1, A2 : 3-Bit Address
D0-D7 :
8-Bit Data
RDn:
Active Low Read Enable
WRn:
Active Low Write Enable
CSn:
Active Low Chip Select
INT:
Interrupt Output
RESET:
Chip Reset
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