參數(shù)資料
型號(hào)： HYS72T128020HU-3S-B
廠商： QIMONDA AG
元件分類(lèi)： DRAM
英文描述： 240-Pin unbuffered DDR2 SDRAM Modules
中文描述： 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
封裝： GREEN, UDIMM-240
文件頁(yè)數(shù)： 24/87頁(yè)
文件大小： 1723K
代理商： HYS72T128020HU-3S-B
Internet Data Sheet
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
24
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
t
DS.BASE
t
DSH
t
DSS
t
HP
100
0.2
0.2
Min(
t
CH.ABS
,
t
CL.ABS
)
—
275
0.6
200
2 x
t
AC.MIN
t
AC.MIN
0
2
0
t
HP
–
t
QHS
—
0.9
0.4
7.5
0.35
0.4
15
7.5
2
7 – AL
—
—
—
—
ps
t
CK.AVG
t
CK.AVG
ps
18)19)20)
17)
17)
21)
Data-out high-impedance time from CK / CK
Address and control input hold time
Control & address input pulse width for each input
t
IPW
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Read preamble
Read postamble
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V. See notes
5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
7) The output timing reference voltage level is
V
TT
.
t
HZ
t
IH.BASE
t
AC.MAX
—
—
—
t
AC.MAX
t
AC.MAX
12
—
12
—
340
1.1
0.6
—
—
0.6
—
—
—
—
ps
ps
t
CK.AVG
ps
ps
ps
ns
nCK
ns
ps
ps
t
CK.AVG
t
CK.AVG
ns
t
CK.AVG
t
CK.AVG
ns
ns
nCK
nCK
9)22)
25)23)
t
IS.BASE
t
LZ.DQ
t
LZ.DQS
t
MOD
t
MRD
t
OIT
t
QH
t
QHS
t
RPRE
t
RPST
t
RTP
t
WPRE
t
WPST
t
WR
t
WTR
t
XARD
t
XARDS
24)25)
9)22)
9)22)
31)
31)
26)
27)
28)29)
28)30)
31)
31)
31)32)
t
XP
2
—
nCK
t
XSNR
t
XSRD
WL
t
RFC
+10
200
RL–1
—
—
ns
nCK
nCK
31)
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
相關(guān)PDF資料
PDF描述
HYS72T128020HU-5-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T64000HU-2.5-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T64000HU-25F-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T64000HU-3.7-B 240-Pin unbuffered DDR2 SDRAM Modules
HYS72T64000HU-3-B 240-Pin unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T128020HU-5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T128020HU-5-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128300HP-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128300HP-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128320HP-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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