參數(shù)資料
型號： HYS72T128000EU-2.5-C2
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 128M X 72 DDR DRAM MODULE, 0.4 ns, DMA240
封裝： GREEN, UDIMM-240
文件頁數(shù)： 19/59頁
文件大?。?/td> 3071K
代理商： HYS72T128000EU-2.5-C2
HYS[64/72]T[128/256]0x0EU–[19F/1.9/25F/2.5/3S]–C2
Unbuffered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.00, 2008-06
26
12032007-I9KE-FFWO
3.6
I
DD Specifications and Conditions
List of tables defining
I
DD Specifications and Conditions.
TABLE 17
I
DD Measurement Conditions
Parameter
Symbol Note
1)2)
3)4)5)
Operating Current 0
One bank Active - Precharge;
t
CK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
I
DD0
Operating Current 1
One bank Active - Read - Precharge;
I
OUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
I
DD1
6)
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
I
DD2N
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
I
DD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
I
DD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN; tCK = tCK.MIN;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
OUT = 0 mA.
I
DD3N
Active Power-Down Current
All banks open;
t
CK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
I
DD3P(0)
Active Power-Down Current
All banks open; t
CK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
I
DD3P(1)
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN; tCK = tCKMIN; tRAS = tRASMAX;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING;
I
OUT = 0mA.
I
DD4R
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
MIN; tCK = tCK.MIN;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
DD4W
Burst Refresh Current
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD5B
Distributed Refresh Current
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD5D
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T128000GR 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
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HYS72T128000GR-5-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules
HYS72T128000HP 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128000HP-2.5-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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