參數(shù)資料
型號(hào): HYS72D32101GR-8-A
廠商: INFINEON TECHNOLOGIES AG
英文描述: Low Profile DDR SDRAM-Modules
中文描述: 超薄DDR內(nèi)存模塊
文件頁(yè)數(shù): 6/29頁(yè)
文件大?。?/td> 803K
代理商: HYS72D32101GR-8-A
HYS72D[16500/32501]GR-[7/8]-A
Low Profile Registered DDR SDRAM-Modules
Overview
Data Sheet
6
Rev. 1.2, 2004-06
10292003-DNYO-BD9L
1
Overview
1.1
Features
184-pin Registered 8 Byte Dual-In-Line DDR SDRAM Module for PC and Server main memory applications
One rank 16M
×
72 and 32M
×
72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single +2.5 V (
±
0.2 V) power
supply
Built with 128 Mbit DDR SDRAMs in 66-Lead TSOPII package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Re-drive for all input signals using register and PLL devices.
Serial Presence Detect with E
2
PROM
JEDEC standard MO-206 form factor:
133.35 mm x 30,48 mm (1.2”) x 4.00 mm
(6,80 mm with stacked components)
JEDEC standard reference layout:
Raw Cards L and M
Gold plated contacts
Table 1
Performance -8/-7
1.2
Description
The HYS 72D
××
0
×
0GR are industry standard 184-pin 8 byte Dual in-line Memory Modules (DIMMs) organized as
16M
×
72 (128 MB)and 32M
×
72 (256 MB). The memory array is designed with Double Data Rate Synchronous
DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the
SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E
2
PROM device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and the second 128 bytes are available to the customer.
Part Number Speed Code
Speed Grade
–7
DDR266A
PC2100-2033
143
133
8
DDR200
PC1600-2022
125
100
Unit
MHz
MHz
Component
Module
@CL2.5
@CL2
max. Clock Frequency
f
CK2.5
f
CK2
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