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參數(shù)資料
| 型號(hào)： | HYS72D32101GR-8-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Low Profile DDR SDRAM-Modules |
| 中文描述： | 超薄DDR內(nèi)存模塊 |
| 文件頁數(shù)： | 28/29頁 |
| 文件大?。?/td> | 803K |
| 代理商： | HYS72D32101GR-8-A |
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HYS72D[16500/32501]GR-[7/8]-A
Low Profile Registered DDR SDRAM-Modules
Application Note
Data Sheet
28
Rev. 1.2, 2004-06
10292003-DNYO-BD9L
a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register inputs to be consistent
with the state of the register outputs.
2. The system switches RESET to a logic 'high' level.
The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous,
it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain
stable).
3. The system must maintain stable register inputs until normal register operation is attained.
The registers have an activation time that allows the clock receivers, input receivers, and output drivers
sufficient time to be turned on and become stable. During this time the system must maintain the valid logic
levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE
outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation
time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept
an input signal, is
t
(ACT ) as specified in the register and DIMM documentation.
4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry/Exit (RESET high, clocks running) — Optional
As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification
explains in detail the method for entering and exiting Self Refresh for this case.
Self Refresh Entry (RESET high, clocks powered off) — Not Permissible
In order to maintain a valid low level on the register output, it is required that either the clocks be running and the
system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the
sequence defined in this application note
.
In the case where RESET remains high and the clocks are powered off,
the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM
state will result.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72D16500GR-7-A | Low Profile DDR SDRAM-Modules |
| HYS72D16500GR | Low Profile DDR SDRAM-Modules |
| HYS72D32501GR-7-A | Low Profile DDR SDRAM-Modules |
| HYS72D16500GR-8-A | Low Profile DDR SDRAM-Modules |
| HYS72D32500GR-7F-B | Low Profile Registered DDR-I SDRAM-Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D32300 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D32300GBR | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D32300GBR-5-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184 - Pin Registered Double Data Rate SDRAM Modules |
| HYS72D32300GBR-5-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D32300GBR-6-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184 - Pin Registered Double Data Rate SDRAM Modules |
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